Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

253222382

1

T1

412366

T2

15726

T3

25

full_word

198338674

1

T1

261202

T2

28707

T3

8

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	451560726	1			T1	673568		T2	44433		T3	33
auto[TlIntgErrCmd]	111	1			T102	3		T119	9		T120	7
auto[TlIntgErrData]	120	1			T102	4		T119	6		T120	10
auto[TlIntgErrBoth]	99	1			T102	3		T119	5		T120	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

238574248

1

T1

345057

T2

30453

T3

1

auto[1]

212986808

1

T1

328511

T2

13980

T3

32

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	151923486	1			T1	244285		T2	9558		T3	1
auto[TlIntgErrNone]	partial	auto[1]	101298598	1			T1	168081		T2	6168		T3	24
auto[TlIntgErrNone]	full_word	auto[0]	86650613	1			T1	100772		T2	20895		T4	71597
auto[TlIntgErrNone]	full_word	auto[1]	111688029	1			T1	160430		T2	7812		T3	8
auto[TlIntgErrCmd]	partial	auto[0]	47	1			T102	1		T119	5		T120	4
auto[TlIntgErrCmd]	partial	auto[1]	55	1			T102	2		T119	4		T120	3
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T178	1		T156	1		T182	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T183	1		T184	1		T185	2
auto[TlIntgErrData]	partial	auto[0]	55	1			T102	2		T119	1		T120	2
auto[TlIntgErrData]	partial	auto[1]	54	1			T102	2		T119	4		T120	5
auto[TlIntgErrData]	full_word	auto[0]	6	1			T120	2		T142	1		T178	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T119	1		T120	1		T178	1
auto[TlIntgErrBoth]	partial	auto[0]	33	1			T102	2		T178	1		T156	1
auto[TlIntgErrBoth]	partial	auto[1]	54	1			T102	1		T119	3		T120	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T156	1		T186	1		T180	1
auto[TlIntgErrBoth]	full_word	auto[1]	9	1			T119	2		T178	1		T156	2