Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_kmac_core.u_key_index_count

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.46 98.55 92.86 100.00 92.00 88.89 u_kmac_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_sha3.u_pad.u_sentmsg_count

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.51 99.38 88.37 94.12 95.70 100.00 u_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_sha3.u_keccak.u_round_count

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
77.06 65.98 100.00 40.00 79.31 100.00 u_keccak


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_count
TotalCoveredPercent
Totals 7 7 100.00
Total Bits 30 30 100.00
Total Bits 0->1 15 15 100.00
Total Bits 1->0 15 15 100.00

Ports 7 7 100.00
Port Bits 30 30 100.00
Port Bits 0->1 15 15 100.00
Port Bits 1->0 15 15 100.00

Port Details
Name   Toggle   Toggle 1->0   Tests   Toggle 0->1   Tests   Direction   
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T17,T28,T5 Yes T1,T2,T3 INPUT
clr_i Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
set_i Unreachable Unreachable Unreachable INPUT
set_cnt_i[4:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[4:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[4:0] Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
cnt_after_commit_o[4:0] Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
err_o Yes Yes T11,T12,T13 Yes T11,T12,T13 OUTPUT

Toggle Coverage for Instance : tb.dut.u_kmac_core.u_key_index_count
TotalCoveredPercent
Totals 7 7 100.00
Total Bits 30 30 100.00
Total Bits 0->1 15 15 100.00
Total Bits 1->0 15 15 100.00

Ports 7 7 100.00
Port Bits 30 30 100.00
Port Bits 0->1 15 15 100.00
Port Bits 1->0 15 15 100.00

Port Details
Name   Toggle   Toggle 1->0   Tests   Toggle 0->1   Tests   Direction   
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T17,T28,T5 Yes T1,T2,T3 INPUT
clr_i Yes Yes T2,T15,T16 Yes T2,T15,T16 INPUT
set_i Unreachable Unreachable Unreachable INPUT
set_cnt_i[4:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T2,T15,T16 Yes T2,T15,T16 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[4:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[4:0] Yes Yes T2,T15,T16 Yes T2,T15,T16 OUTPUT
cnt_after_commit_o[4:0] Yes Yes T2,T15,T16 Yes T2,T15,T16 OUTPUT
err_o Yes Yes T11,T12,T13 Yes T11,T12,T13 OUTPUT

Toggle Coverage for Instance : tb.dut.u_sha3.u_pad.u_sentmsg_count
TotalCoveredPercent
Totals 7 7 100.00
Total Bits 30 30 100.00
Total Bits 0->1 15 15 100.00
Total Bits 1->0 15 15 100.00

Ports 7 7 100.00
Port Bits 30 30 100.00
Port Bits 0->1 15 15 100.00
Port Bits 1->0 15 15 100.00

Port Details
Name   Toggle   Toggle 1->0   Tests   Toggle 0->1   Tests   Direction   
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T17,T28,T5 Yes T1,T2,T3 INPUT
clr_i Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
set_i Unreachable Unreachable Unreachable INPUT
set_cnt_i[4:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[4:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[4:0] Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
cnt_after_commit_o[4:0] Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
err_o Yes Yes T11,T12,T13 Yes T11,T12,T13 OUTPUT

Toggle Coverage for Instance : tb.dut.u_sha3.u_keccak.u_round_count
TotalCoveredPercent
Totals 7 7 100.00
Total Bits 30 30 100.00
Total Bits 0->1 15 15 100.00
Total Bits 1->0 15 15 100.00

Ports 7 7 100.00
Port Bits 30 30 100.00
Port Bits 0->1 15 15 100.00
Port Bits 1->0 15 15 100.00

Port Details
Name   Toggle   Toggle 1->0   Tests   Toggle 0->1   Tests   Direction   
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T17,T28,T5 Yes T1,T2,T3 INPUT
clr_i Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
set_i Unreachable Unreachable Unreachable INPUT
set_cnt_i[4:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[4:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[4:0] Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
cnt_after_commit_o[4:0] Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
err_o Yes Yes T11,T12,T13 Yes T11,T12,T13 OUTPUT