SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.sha3pad_assert_cov_if | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
97.24 | 96.27 | 93.33 | 100.00 | 100.00 | 93.85 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
ProcessToRun_A | 2147483647 | 347200 | 0 | 0 |
RunThenComplete_M | 2147483647 | 3060448 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 347200 | 0 | 0 |
T1 | 137897 | 310 | 0 | 0 |
T2 | 520718 | 65 | 0 | 0 |
T3 | 1007 | 0 | 0 | 0 |
T4 | 420329 | 246 | 0 | 0 |
T14 | 793137 | 374 | 0 | 0 |
T15 | 332633 | 160 | 0 | 0 |
T16 | 433650 | 154 | 0 | 0 |
T17 | 436181 | 114 | 0 | 0 |
T18 | 136605 | 310 | 0 | 0 |
T19 | 0 | 374 | 0 | 0 |
T20 | 0 | 13 | 0 | 0 |
T21 | 1373 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 3060448 | 0 | 0 |
T1 | 137897 | 5462 | 0 | 0 |
T2 | 520718 | 312 | 0 | 0 |
T3 | 1007 | 0 | 0 | 0 |
T4 | 420329 | 5427 | 0 | 0 |
T14 | 793137 | 5526 | 0 | 0 |
T15 | 332633 | 386 | 0 | 0 |
T16 | 433650 | 798 | 0 | 0 |
T17 | 436181 | 1800 | 0 | 0 |
T18 | 136605 | 5462 | 0 | 0 |
T19 | 0 | 5526 | 0 | 0 |
T20 | 0 | 65 | 0 | 0 |
T21 | 1373 | 0 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |