Module Definition
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Module : prim_subreg
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg.u_intr_state_fifo_empty 65.24 85.71 50.00 60.00
tb.dut.u_reg.u_entropy_refresh_hash_cnt 65.24 85.71 50.00 60.00
tb.dut.u_reg.u_intr_state_kmac_done 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_state_kmac_err 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_kmac_done 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_fifo_empty 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_kmac_err 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_kmac_en.staged_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_kmac_en.shadow_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_kmac_en.committed_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_kstrength.staged_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_kstrength.shadow_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_kstrength.committed_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_mode.staged_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_mode.shadow_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_mode.committed_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_msg_endianness.staged_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_msg_endianness.shadow_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_msg_endianness.committed_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_state_endianness.staged_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_state_endianness.shadow_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_state_endianness.committed_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_sideload.staged_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_sideload.shadow_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_sideload.committed_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_mode.staged_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_mode.shadow_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_mode.committed_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_fast_process.staged_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_fast_process.shadow_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_fast_process.committed_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_msg_mask.staged_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_msg_mask.shadow_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_msg_mask.committed_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_ready.staged_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_ready.shadow_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_ready.committed_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_en_unsupported_modestrength.staged_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_en_unsupported_modestrength.shadow_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_en_unsupported_modestrength.committed_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_entropy_period_prescaler 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_entropy_period_wait_timer 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_entropy_refresh_threshold_shadowed.staged_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_entropy_refresh_threshold_shadowed.shadow_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_entropy_refresh_threshold_shadowed.committed_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_key_len 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_prefix_0 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_prefix_1 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_prefix_2 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_prefix_3 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_prefix_4 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_prefix_5 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_prefix_6 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_prefix_7 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_prefix_8 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_prefix_9 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_prefix_10 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_err_code 100.00 100.00 100.00 100.00

Line Coverage for Module : prim_subreg
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Module : prim_subreg ( parameter DW=32,SwAccess=0,RESVAL=0,Mubi=0 + DW=32,SwAccess=1,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_prefix_0

SCORECOND
100.00 100.00
tb.dut.u_reg.u_prefix_1

SCORECOND
100.00 100.00
tb.dut.u_reg.u_prefix_2

SCORECOND
100.00 100.00
tb.dut.u_reg.u_prefix_3

SCORECOND
100.00 100.00
tb.dut.u_reg.u_prefix_4

SCORECOND
100.00 100.00
tb.dut.u_reg.u_prefix_5

SCORECOND
100.00 100.00
tb.dut.u_reg.u_prefix_6

SCORECOND
100.00 100.00
tb.dut.u_reg.u_prefix_7

SCORECOND
100.00 100.00
tb.dut.u_reg.u_prefix_8

SCORECOND
100.00 100.00
tb.dut.u_reg.u_prefix_9

SCORECOND
100.00 100.00
tb.dut.u_reg.u_prefix_10

SCORECOND
100.00 100.00
tb.dut.u_reg.u_err_code

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T15,T16

Cond Coverage for Module : prim_subreg ( parameter DW=2,SwAccess=0,RESVAL,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_mode.staged_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_mode.shadow_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_mode.committed_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_mode.staged_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_mode.shadow_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_mode.committed_reg

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

Cond Coverage for Module : prim_subreg ( parameter DW=10,SwAccess=0,RESVAL,Mubi=0 + DW=10,SwAccess=1,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_entropy_period_prescaler

SCORECOND
100.00 100.00
tb.dut.u_reg.u_entropy_refresh_threshold_shadowed.staged_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_entropy_refresh_threshold_shadowed.shadow_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_entropy_refresh_threshold_shadowed.committed_reg

SCORECOND
65.24 50.00
tb.dut.u_reg.u_entropy_refresh_hash_cnt

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : prim_subreg ( parameter DW=16,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_entropy_period_wait_timer

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

Cond Coverage for Module : prim_subreg ( parameter DW=3,SwAccess=0,RESVAL,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_kstrength.staged_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_kstrength.shadow_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_kstrength.committed_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_key_len

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

Cond Coverage for Module : prim_subreg ( parameter DW=1,SwAccess=3,RESVAL=0,Mubi=0 + DW=1,SwAccess=1,RESVAL=0,Mubi=0 + DW=1,SwAccess=0,RESVAL,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_kmac_done

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_kmac_err

SCORECOND
65.24 50.00
tb.dut.u_reg.u_intr_state_fifo_empty

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_kmac_done

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_fifo_empty

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_kmac_err

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_kmac_en.staged_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_kmac_en.shadow_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_kmac_en.committed_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_msg_endianness.staged_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_msg_endianness.shadow_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_msg_endianness.committed_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_state_endianness.staged_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_state_endianness.shadow_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_state_endianness.committed_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_sideload.staged_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_sideload.shadow_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_sideload.committed_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_fast_process.staged_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_fast_process.shadow_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_fast_process.committed_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_msg_mask.staged_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_msg_mask.shadow_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_msg_mask.committed_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_ready.staged_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_ready.shadow_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_ready.committed_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_en_unsupported_modestrength.staged_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_en_unsupported_modestrength.shadow_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_en_unsupported_modestrength.committed_reg

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Module : prim_subreg
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%