Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	38440	0	0
entropy_period_rd_A	2147483647	1795	0	0
intr_enable_rd_A	2147483647	2477	0	0
prefix_0_rd_A	2147483647	1979	0	0
prefix_10_rd_A	2147483647	2030	0	0
prefix_1_rd_A	2147483647	1976	0	0
prefix_2_rd_A	2147483647	2040	0	0
prefix_3_rd_A	2147483647	1745	0	0
prefix_4_rd_A	2147483647	2076	0	0
prefix_5_rd_A	2147483647	1929	0	0
prefix_6_rd_A	2147483647	1967	0	0
prefix_7_rd_A	2147483647	2070	0	0
prefix_8_rd_A	2147483647	2050	0	0
prefix_9_rd_A	2147483647	1937	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	38440	0	0
T48	315654	35457	0	0
T49	0	50	0	0
T50	0	97	0	0
T102	0	2	0	0
T119	0	1	0	0
T120	0	3	0	0
T123	0	27	0	0
T129	0	16	0	0
T132	0	5	0	0
T133	25385	0	0	0
T134	159206	0	0	0
T135	137856	0	0	0
T136	170840	0	0	0
T137	16453	0	0	0
T138	6292	0	0	0
T139	952757	0	0	0
T140	256408	0	0	0
T141	16595	0	0	0
T142	0	1	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1795	0	0
T103	6715	30	0	0
T105	3878	5	0	0
T106	10536	38	0	0
T142	11241	56	0	0
T151	144274	201	0	0
T152	14330	97	0	0
T153	5697	5	0	0
T154	6105	36	0	0
T155	11159	55	0	0
T156	23523	79	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2477	0	0
T103	6715	17	0	0
T124	972	13	0	0
T142	11241	75	0	0
T151	144274	451	0	0
T152	14330	99	0	0
T153	5697	34	0	0
T157	1905	5	0	0
T158	1459	25	0	0
T159	1146	9	0	0
T160	1039	16	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1979	0	0
T103	6715	20	0	0
T105	3878	4	0	0
T106	10536	26	0	0
T142	11241	48	0	0
T151	144274	480	0	0
T152	14330	63	0	0
T153	5697	17	0	0
T154	6105	42	0	0
T155	11159	45	0	0
T156	23523	59	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2030	0	0
T103	6715	15	0	0
T105	3878	2	0	0
T106	10536	36	0	0
T142	11241	53	0	0
T151	144274	469	0	0
T152	14330	76	0	0
T153	5697	9	0	0
T154	6105	24	0	0
T155	11159	35	0	0
T156	23523	112	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1976	0	0
T103	6715	19	0	0
T105	3878	9	0	0
T106	10536	24	0	0
T142	11241	47	0	0
T151	144274	377	0	0
T152	14330	60	0	0
T153	5697	18	0	0
T154	6105	13	0	0
T155	11159	21	0	0
T161	1834	1	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2040	0	0
T103	6715	20	0	0
T105	3878	3	0	0
T106	10536	37	0	0
T142	11241	47	0	0
T151	144274	480	0	0
T152	14330	69	0	0
T153	5697	18	0	0
T154	6105	22	0	0
T155	11159	32	0	0
T156	23523	58	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1745	0	0
T103	6715	17	0	0
T105	3878	10	0	0
T106	10536	27	0	0
T142	11241	25	0	0
T151	144274	444	0	0
T152	14330	53	0	0
T153	5697	5	0	0
T154	6105	25	0	0
T155	11159	21	0	0
T156	23523	80	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2076	0	0
T103	6715	25	0	0
T105	3878	6	0	0
T106	10536	43	0	0
T142	11241	33	0	0
T151	144274	482	0	0
T152	14330	63	0	0
T153	5697	10	0	0
T154	6105	30	0	0
T155	11159	77	0	0
T161	1834	7	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1929	0	0
T103	6715	14	0	0
T105	3878	7	0	0
T106	10536	15	0	0
T142	11241	29	0	0
T151	144274	451	0	0
T152	14330	61	0	0
T153	5697	16	0	0
T154	6105	82	0	0
T155	11159	35	0	0
T156	23523	91	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1967	0	0
T103	6715	18	0	0
T105	3878	5	0	0
T106	10536	14	0	0
T142	11241	39	0	0
T151	144274	475	0	0
T152	14330	75	0	0
T153	5697	10	0	0
T154	6105	25	0	0
T155	11159	9	0	0
T156	23523	66	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2070	0	0
T103	6715	19	0	0
T105	3878	6	0	0
T106	10536	28	0	0
T142	11241	41	0	0
T151	144274	454	0	0
T152	14330	52	0	0
T153	5697	20	0	0
T154	6105	44	0	0
T155	11159	45	0	0
T161	1834	4	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2050	0	0
T103	6715	22	0	0
T105	3878	17	0	0
T106	10536	51	0	0
T142	11241	41	0	0
T151	144274	454	0	0
T152	14330	71	0	0
T153	5697	17	0	0
T154	6105	48	0	0
T155	11159	29	0	0
T156	23523	88	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1937	0	0
T103	6715	14	0	0
T106	10536	24	0	0
T142	11241	52	0	0
T151	144274	437	0	0
T152	14330	69	0	0
T153	5697	25	0	0
T154	6105	29	0	0
T155	11159	30	0	0
T156	23523	84	0	0
T161	1834	4	0	0