Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	253848319	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

200695380

1

T1

887917

T2

39394

T3

151701

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	239668017	1			T1	112203		T2	41171		T3	60881
values[0x0]	103302877	1			T1	451957		T2	8599		T3	59616
values[0x1]	111572805	1			T1	492650		T2	8809		T3	59483

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	197930731	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

256612968

1

T1

114907

T2

43560

T3

159129

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1379351	1			T1	8275		T2	202		T3	713
valid_sources[0x01]	1466737	1			T1	8222		T2	241		T3	738
valid_sources[0x02]	2237010	1			T1	8182		T2	217		T3	769
valid_sources[0x03]	1373734	1			T1	7969		T2	225		T3	750
valid_sources[0x04]	2233817	1			T1	8235		T2	234		T3	764
valid_sources[0x05]	1365775	1			T1	8185		T2	218		T3	720
valid_sources[0x06]	1368518	1			T1	7986		T2	261		T3	732
valid_sources[0x07]	1529634	1			T1	8217		T2	196		T3	669
valid_sources[0x08]	1366293	1			T1	7854		T2	194		T3	628
valid_sources[0x09]	1437627	1			T1	7955		T2	240		T3	670
valid_sources[0x0a]	5510748	1			T1	7875		T2	215		T3	810
valid_sources[0x0b]	3431657	1			T1	8116		T2	239		T3	778
valid_sources[0x0c]	3415270	1			T1	8264		T2	209		T3	783
valid_sources[0x0d]	1370273	1			T1	7970		T2	232		T3	671
valid_sources[0x0e]	2036274	1			T1	7923		T2	240		T3	678
valid_sources[0x0f]	1370579	1			T1	8112		T2	224		T3	592
valid_sources[0x10]	1366716	1			T1	8016		T2	230		T3	655
valid_sources[0x11]	3817783	1			T1	8505		T2	237		T3	640
valid_sources[0x12]	2149025	1			T1	8192		T2	232		T3	784
valid_sources[0x13]	1371678	1			T1	8226		T2	261		T3	774
valid_sources[0x14]	1368821	1			T1	8063		T2	221		T3	861
valid_sources[0x15]	2273856	1			T1	8270		T2	229		T3	715
valid_sources[0x16]	1425995	1			T1	7840		T2	216		T3	727
valid_sources[0x17]	2286749	1			T1	8207		T2	211		T3	568
valid_sources[0x18]	1366112	1			T1	8051		T2	246		T3	637
valid_sources[0x19]	1430781	1			T1	7717		T2	210		T3	594
valid_sources[0x1a]	1429876	1			T1	7968		T2	217		T3	791
valid_sources[0x1b]	1369909	1			T1	8161		T2	240		T3	741
valid_sources[0x1c]	1378613	1			T1	8070		T2	240		T3	645
valid_sources[0x1d]	1370020	1			T1	8112		T2	196		T3	763
valid_sources[0x1e]	1373939	1			T1	7917		T2	238		T3	772
valid_sources[0x1f]	1371912	1			T1	7905		T2	255		T3	678
valid_sources[0x20]	3747938	1			T1	7878		T2	218		T3	693
valid_sources[0x21]	1442987	1			T1	8180		T2	219		T3	652
valid_sources[0x22]	1996585	1			T1	8135		T2	241		T3	739
valid_sources[0x23]	1372856	1			T1	8049		T2	225		T3	796
valid_sources[0x24]	1374045	1			T1	7972		T2	204		T3	692
valid_sources[0x25]	2297943	1			T1	8103		T2	237		T3	805
valid_sources[0x26]	1963752	1			T1	8209		T2	210		T3	764
valid_sources[0x27]	2244935	1			T1	7945		T2	236		T3	632
valid_sources[0x28]	1375421	1			T1	7981		T2	245		T3	689
valid_sources[0x29]	3413084	1			T1	8472		T2	240		T3	767
valid_sources[0x2a]	1403285	1			T1	7716		T2	232		T3	725
valid_sources[0x2b]	1369043	1			T1	8208		T2	215		T3	647
valid_sources[0x2c]	1374326	1			T1	8189		T2	195		T3	707
valid_sources[0x2d]	1368662	1			T1	8058		T2	229		T3	648
valid_sources[0x2e]	1371221	1			T1	8088		T2	212		T3	615
valid_sources[0x2f]	1419788	1			T1	7960		T2	213		T3	769
valid_sources[0x30]	1424784	1			T1	8093		T2	239		T3	701
valid_sources[0x31]	1415755	1			T1	7932		T2	204		T3	703
valid_sources[0x32]	1373885	1			T1	8204		T2	228		T3	739
valid_sources[0x33]	1374639	1			T1	8000		T2	214		T3	689
valid_sources[0x34]	1368345	1			T1	8090		T2	225		T3	735
valid_sources[0x35]	2256825	1			T1	8239		T2	235		T3	558
valid_sources[0x36]	1368141	1			T1	8078		T2	227		T3	795
valid_sources[0x37]	2217932	1			T1	8189		T2	221		T3	664
valid_sources[0x38]	1368712	1			T1	8152		T2	247		T3	811
valid_sources[0x39]	1366088	1			T1	8246		T2	258		T3	679
valid_sources[0x3a]	1369364	1			T1	7995		T2	274		T3	647
valid_sources[0x3b]	1373858	1			T1	8273		T2	246		T3	656
valid_sources[0x3c]	1825693	1			T1	8155		T2	227		T3	617
valid_sources[0x3d]	4945922	1			T1	8296		T2	215		T3	721
valid_sources[0x3e]	1373547	1			T1	7959		T2	220		T3	615
valid_sources[0x3f]	1376412	1			T1	8087		T2	243		T3	771
valid_sources[0x40]	2029959	1			T1	7892		T2	247		T3	581
valid_sources[0x41]	2322401	1			T1	8181		T2	240		T3	773
valid_sources[0x42]	2040461	1			T1	8009		T2	245		T3	691
valid_sources[0x43]	1371019	1			T1	7890		T2	208		T3	756
valid_sources[0x44]	1391043	1			T1	7999		T2	283		T3	802
valid_sources[0x45]	1906505	1			T1	7969		T2	197		T3	747
valid_sources[0x46]	2406879	1			T1	8062		T2	231		T3	798
valid_sources[0x47]	1365365	1			T1	8237		T2	216		T3	719
valid_sources[0x48]	1371779	1			T1	7825		T2	204		T3	731
valid_sources[0x49]	1371510	1			T1	8191		T2	251		T3	682
valid_sources[0x4a]	1390645	1			T1	8078		T2	254		T3	673
valid_sources[0x4b]	2285850	1			T1	8030		T2	221		T3	716
valid_sources[0x4c]	2274351	1			T1	8014		T2	263		T3	826
valid_sources[0x4d]	1368017	1			T1	8086		T2	197		T3	742
valid_sources[0x4e]	1511903	1			T1	7826		T2	210		T3	738
valid_sources[0x4f]	1376600	1			T1	7763		T2	243		T3	681
valid_sources[0x50]	1375672	1			T1	7826		T2	202		T3	649
valid_sources[0x51]	3763462	1			T1	8052		T2	240		T3	729
valid_sources[0x52]	1374775	1			T1	7908		T2	244		T3	739
valid_sources[0x53]	1407728	1			T1	8149		T2	233		T3	621
valid_sources[0x54]	1374538	1			T1	8262		T2	211		T3	640
valid_sources[0x55]	1375101	1			T1	8119		T2	263		T3	804
valid_sources[0x56]	1492555	1			T1	8184		T2	235		T3	679
valid_sources[0x57]	1379439	1			T1	8046		T2	217		T3	591
valid_sources[0x58]	3187395	1			T1	7970		T2	232		T3	707
valid_sources[0x59]	1457983	1			T1	7986		T2	236		T3	624
valid_sources[0x5a]	1373585	1			T1	8179		T2	250		T3	735
valid_sources[0x5b]	1374710	1			T1	8232		T2	225		T3	657
valid_sources[0x5c]	1371784	1			T1	8207		T2	211		T3	721
valid_sources[0x5d]	1371576	1			T1	8181		T2	217		T3	617
valid_sources[0x5e]	1374584	1			T1	8215		T2	237		T3	690
valid_sources[0x5f]	2035125	1			T1	8051		T2	212		T3	708
valid_sources[0x60]	1368505	1			T1	8016		T2	242		T3	695
valid_sources[0x61]	1370724	1			T1	8000		T2	208		T3	693
valid_sources[0x62]	1370096	1			T1	7987		T2	218		T3	566
valid_sources[0x63]	1370758	1			T1	7926		T2	261		T3	682
valid_sources[0x64]	1763079	1			T1	7939		T2	245		T3	569
valid_sources[0x65]	3778865	1			T1	8012		T2	256		T3	701
valid_sources[0x66]	1941446	1			T1	7963		T2	263		T3	644
valid_sources[0x67]	1416412	1			T1	7898		T2	238		T3	635
valid_sources[0x68]	3406498	1			T1	8071		T2	225		T3	621
valid_sources[0x69]	1464823	1			T1	8040		T2	256		T3	688
valid_sources[0x6a]	1488865	1			T1	8260		T2	213		T3	748
valid_sources[0x6b]	3444678	1			T1	8197		T2	238		T3	840
valid_sources[0x6c]	1367921	1			T1	7994		T2	225		T3	652
valid_sources[0x6d]	1368890	1			T1	7837		T2	203		T3	690
valid_sources[0x6e]	1373515	1			T1	7945		T2	188		T3	746
valid_sources[0x6f]	1393209	1			T1	7948		T2	215		T3	691
valid_sources[0x70]	3824683	1			T1	8347		T2	232		T3	759
valid_sources[0x71]	3421067	1			T1	8246		T2	236		T3	666
valid_sources[0x72]	1534404	1			T1	8395		T2	216		T3	609
valid_sources[0x73]	1405162	1			T1	8209		T2	254		T3	749
valid_sources[0x74]	1374235	1			T1	8340		T2	229		T3	798
valid_sources[0x75]	3401626	1			T1	8227		T2	206		T3	656
valid_sources[0x76]	1401597	1			T1	8101		T2	237		T3	744
valid_sources[0x77]	1369816	1			T1	7961		T2	280		T3	700
valid_sources[0x78]	1663980	1			T1	8134		T2	242		T3	651
valid_sources[0x79]	2025365	1			T1	7923		T2	220		T3	738
valid_sources[0x7a]	1366155	1			T1	8132		T2	202		T3	708
valid_sources[0x7b]	2242352	1			T1	7963		T2	191		T3	605
valid_sources[0x7c]	1485629	1			T1	7979		T2	248		T3	669
valid_sources[0x7d]	3935584	1			T1	8103		T2	232		T3	740
valid_sources[0x7e]	1368873	1			T1	8156		T2	217		T3	726
valid_sources[0x7f]	1371688	1			T1	7989		T2	221		T3	650
valid_sources[0x80]	3787870	1			T1	7784		T2	250		T3	720

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

87376559

1

T1

421690

T2

29214

T3

34200

values[0x0]

all_enables

biggest_size

60945360

1

T1

253076

T2

5514

T3

58897

values[0x1]

all_enables

biggest_size

52373461

1

T1

213151

T2

4666

T3

58604