Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

253862017

1

T1

117872

T2

19185

T3

28279

full_word

200696262

1

T1

887917

T2

39394

T3

151701

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	454557969	1			T1	206664		T2	58579		T3	179980
auto[TlIntgErrCmd]	96	1			T115	3		T118	9		T119	6
auto[TlIntgErrData]	106	1			T115	5		T118	5		T119	7
auto[TlIntgErrBoth]	108	1			T115	2		T118	6		T119	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

239670433

1

T1

112203

T2

41171

T3

60881

auto[1]

214887846

1

T1

944607

T2

17408

T3

119099

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	152293522	1			T1	700345		T2	11957		T3	26681
auto[TlIntgErrNone]	partial	auto[1]	101568215	1			T1	478380		T2	7228		T3	1598
auto[TlIntgErrNone]	full_word	auto[0]	87376767	1			T1	421690		T2	29214		T3	34200
auto[TlIntgErrNone]	full_word	auto[1]	113319465	1			T1	466227		T2	10180		T3	117501
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T115	2		T118	2		T119	2
auto[TlIntgErrCmd]	partial	auto[1]	46	1			T115	1		T118	6		T119	4
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T118	1		T172	1		T173	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T174	1		T175	1		T176	2
auto[TlIntgErrData]	partial	auto[0]	44	1			T115	3		T118	2		T119	3
auto[TlIntgErrData]	partial	auto[1]	48	1			T115	2		T118	2		T119	3
auto[TlIntgErrData]	full_word	auto[0]	6	1			T118	1		T171	1		T177	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T119	1		T140	1		T178	1
auto[TlIntgErrBoth]	partial	auto[0]	43	1			T115	2		T118	2		T119	3
auto[TlIntgErrBoth]	partial	auto[1]	56	1			T118	4		T119	4		T137	5
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T171	1		T178	1		T174	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T137	1		T174	1		T179	1