Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_arbiter_fixed
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.05 87.50 92.68 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_app_intf.u_appid_arb 95.05 87.50 92.68 100.00 100.00



Module Instance : tb.dut.u_app_intf.u_appid_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.05 87.50 92.68 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.05 87.50 92.68 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
80.49 90.99 84.93 40.00 86.52 100.00 u_app_intf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_arbiter_fixed
Line No.TotalCoveredPercent
TOTAL322887.50
CONT_ASSIGN8511100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN87100.00
CONT_ASSIGN87100.00
CONT_ASSIGN87100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9711100.00
ALWAYS10566100.00
ALWAYS10566100.00
ALWAYS10566100.00
CONT_ASSIGN124100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12911100.00
CONT_ASSIGN13211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
85 3 3
87 0 3
89 3 3
97 1 1
105 1 1
107 1 1
109 1 1
110 1 1
112 1 1
113 1 1
105 1 1
107 1 1
109 1 1
110 1 1
112 1 1
113 1 1
105 1 1
107 1 1
109 1 1
110 1 1
112 1 1
113 1 1
124 0 1
128 1 1
129 1 1
132 1 1


Cond Coverage for Module : prim_arbiter_fixed
TotalCoveredPercent
Conditions413892.68
Logical413892.68
Non-Logical00
Event00

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT2,T13,T16
01CoveredT2,T13,T16
10CoveredT2,T13,T16

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT2,T13,T16
01CoveredT2,T13,T16
10CoveredT2,T13,T16

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT2,T13,T16
01Unreachable
10CoveredT2,T13,T16

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT2,T13,T16
1CoveredT2,T13,T16

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1-StatusTests
0CoveredT2,T13,T16
1CoveredT2,T13,T16

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1-StatusTests
0CoveredT2,T13,T16
1CoveredT2,T13,T16

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT2,T13,T16
1CoveredT2,T13,T16

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1-StatusTests
0CoveredT2,T13,T16
1CoveredT2,T13,T16

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1-StatusTests
0CoveredT2,T13,T16
1CoveredT2,T13,T16

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT2,T13,T16
10CoveredT2,T13,T16
11CoveredT2,T13,T16

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT2,T13,T16
10CoveredT2,T13,T16
11CoveredT2,T13,T16

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT2,T13,T16
10Not Covered
11CoveredT2,T13,T16

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT2,T13,T16
10CoveredT2,T13,T16
11CoveredT2,T13,T16

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT2,T13,T16
10CoveredT2,T13,T16
11CoveredT2,T13,T16

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT2,T13,T16
10CoveredT2,T13,T16
11Not Covered

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---
-1--2-StatusTests
01Not Covered
10CoveredT2,T13,T16
11CoveredT2,T13,T16

Branch Coverage for Module : prim_arbiter_fixed
Line No.TotalCoveredPercent
Branches 12 12 100.00
TERNARY 109 2 2 100.00
TERNARY 110 2 2 100.00
TERNARY 109 2 2 100.00
TERNARY 110 2 2 100.00
TERNARY 109 2 2 100.00
TERNARY 110 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T2,T13,T16
0 Covered T2,T13,T16


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T2,T13,T16
0 Covered T2,T13,T16


LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T2,T13,T16
0 Covered T2,T13,T16


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T2,T13,T16
0 Covered T2,T13,T16


LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T2,T13,T16
0 Covered T2,T13,T16


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T2,T13,T16
0 Covered T2,T13,T16


Assert Coverage for Module : prim_arbiter_fixed
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 13 13 100.00 13 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 13 13 100.00 13 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckHotOne_A 2147483647 2147483647 0 0
CheckNGreaterZero_A 1024 1024 0 0
GntImpliesReady_A 2147483647 6637 0 0
GntImpliesValid_A 2147483647 6637 0 0
GrantKnown_A 2147483647 2147483647 0 0
IdxKnown_A 2147483647 2147483647 0 0
IndexIsCorrect_A 2147483647 6637 0 0
NoReadyValidNoGrant_A 2147483647 2147483647 0 0
Priority_A 2147483647 1975832 0 0
ReadyAndValidImplyGrant_A 2147483647 6637 0 0
ReqAndReadyImplyGrant_A 2147483647 6637 0 0
ReqImpliesValid_A 2147483647 1975832 0 0
ValidKnown_A 2147483647 2147483647 0 0


CheckHotOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 436231 436224 0 0
T2 612936 612886 0 0
T3 370529 370452 0 0
T13 124664 124654 0 0
T14 175526 175519 0 0
T15 470234 470226 0 0
T16 180334 180262 0 0
T17 182788 182779 0 0
T18 595150 595051 0 0
T19 205866 205800 0 0

CheckNGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1024 1024 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

GntImpliesReady_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 6637 0 0
T2 612936 31 0 0
T3 370529 0 0 0
T13 124664 7 0 0
T14 175526 0 0 0
T15 470234 0 0 0
T16 180334 25 0 0
T17 182788 0 0 0
T18 595150 25 0 0
T19 205866 101 0 0
T20 0 7 0 0
T23 0 26 0 0
T27 0 7 0 0
T37 149533 0 0 0
T38 0 26 0 0
T39 0 74 0 0

GntImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 6637 0 0
T2 612936 31 0 0
T3 370529 0 0 0
T13 124664 7 0 0
T14 175526 0 0 0
T15 470234 0 0 0
T16 180334 25 0 0
T17 182788 0 0 0
T18 595150 25 0 0
T19 205866 101 0 0
T20 0 7 0 0
T23 0 26 0 0
T27 0 7 0 0
T37 149533 0 0 0
T38 0 26 0 0
T39 0 74 0 0

GrantKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 436231 436224 0 0
T2 612936 612886 0 0
T3 370529 370452 0 0
T13 124664 124654 0 0
T14 175526 175519 0 0
T15 470234 470226 0 0
T16 180334 180262 0 0
T17 182788 182779 0 0
T18 595150 595051 0 0
T19 205866 205800 0 0

IdxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 436231 436224 0 0
T2 612936 612886 0 0
T3 370529 370452 0 0
T13 124664 124654 0 0
T14 175526 175519 0 0
T15 470234 470226 0 0
T16 180334 180262 0 0
T17 182788 182779 0 0
T18 595150 595051 0 0
T19 205866 205800 0 0

IndexIsCorrect_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 6637 0 0
T2 612936 31 0 0
T3 370529 0 0 0
T13 124664 7 0 0
T14 175526 0 0 0
T15 470234 0 0 0
T16 180334 25 0 0
T17 182788 0 0 0
T18 595150 25 0 0
T19 205866 101 0 0
T20 0 7 0 0
T23 0 26 0 0
T27 0 7 0 0
T37 149533 0 0 0
T38 0 26 0 0
T39 0 74 0 0

NoReadyValidNoGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 436231 436224 0 0
T2 612936 608911 0 0
T3 370529 370452 0 0
T13 124664 124589 0 0
T14 175526 175519 0 0
T15 470234 470226 0 0
T16 180334 178613 0 0
T17 182788 182779 0 0
T18 595150 593379 0 0
T19 205866 193415 0 0

Priority_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1975832 0 0
T2 612936 3975 0 0
T3 370529 0 0 0
T4 0 2568 0 0
T13 124664 645 0 0
T14 175526 0 0 0
T15 470234 0 0 0
T16 180334 1649 0 0
T17 182788 0 0 0
T18 595150 1672 0 0
T19 205866 12385 0 0
T20 0 300 0 0
T23 0 4138 0 0
T27 0 1438 0 0
T37 149533 0 0 0
T38 0 3637 0 0

ReadyAndValidImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 6637 0 0
T2 612936 31 0 0
T3 370529 0 0 0
T13 124664 7 0 0
T14 175526 0 0 0
T15 470234 0 0 0
T16 180334 25 0 0
T17 182788 0 0 0
T18 595150 25 0 0
T19 205866 101 0 0
T20 0 7 0 0
T23 0 26 0 0
T27 0 7 0 0
T37 149533 0 0 0
T38 0 26 0 0
T39 0 74 0 0

ReqAndReadyImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 6637 0 0
T2 612936 31 0 0
T3 370529 0 0 0
T13 124664 7 0 0
T14 175526 0 0 0
T15 470234 0 0 0
T16 180334 25 0 0
T17 182788 0 0 0
T18 595150 25 0 0
T19 205866 101 0 0
T20 0 7 0 0
T23 0 26 0 0
T27 0 7 0 0
T37 149533 0 0 0
T38 0 26 0 0
T39 0 74 0 0

ReqImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1975832 0 0
T2 612936 3975 0 0
T3 370529 0 0 0
T4 0 2568 0 0
T13 124664 645 0 0
T14 175526 0 0 0
T15 470234 0 0 0
T16 180334 1649 0 0
T17 182788 0 0 0
T18 595150 1672 0 0
T19 205866 12385 0 0
T20 0 300 0 0
T23 0 4138 0 0
T27 0 1438 0 0
T37 149533 0 0 0
T38 0 3637 0 0

ValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 436231 436224 0 0
T2 612936 612886 0 0
T3 370529 370452 0 0
T13 124664 124654 0 0
T14 175526 175519 0 0
T15 470234 470226 0 0
T16 180334 180262 0 0
T17 182788 182779 0 0
T18 595150 595051 0 0
T19 205866 205800 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%