Module Definition
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Module : keccak_2share
SCORELINECONDTOGGLEFSMBRANCHASSERT
81.25 100.00 75.00 50.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/keccak_2share.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_sha3.u_keccak.u_keccak_p 81.25 100.00 75.00 50.00 100.00



Module Instance : tb.dut.u_sha3.u_keccak.u_keccak_p

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
81.25 100.00 75.00 50.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
81.25 100.00 75.00 50.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
77.06 65.98 100.00 40.00 79.31 100.00 u_keccak


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : keccak_2share
Line No.TotalCoveredPercent
TOTAL7373100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9100
CONT_ASSIGN9811100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN11411100.00
CONT_ASSIGN11511100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN12511100.00
CONT_ASSIGN12911100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN14311100.00
CONT_ASSIGN29611100.00
CONT_ASSIGN29711100.00
CONT_ASSIGN31411100.00
CONT_ASSIGN31511100.00
CONT_ASSIGN32211100.00
CONT_ASSIGN32411100.00
CONT_ASSIGN32411100.00
CONT_ASSIGN32411100.00
CONT_ASSIGN32411100.00
CONT_ASSIGN32411100.00
CONT_ASSIGN32411100.00
CONT_ASSIGN32411100.00
CONT_ASSIGN32411100.00
CONT_ASSIGN32411100.00
CONT_ASSIGN32411100.00
CONT_ASSIGN32411100.00
CONT_ASSIGN32411100.00
CONT_ASSIGN32411100.00
CONT_ASSIGN32411100.00
CONT_ASSIGN32411100.00
CONT_ASSIGN32411100.00
CONT_ASSIGN32411100.00
CONT_ASSIGN32411100.00
CONT_ASSIGN32411100.00
CONT_ASSIGN32411100.00
CONT_ASSIGN32411100.00
CONT_ASSIGN32411100.00
CONT_ASSIGN32411100.00
CONT_ASSIGN32411100.00
CONT_ASSIGN34411100.00
ROUTINE36300
ROUTINE36355100.00
ROUTINE37600
ROUTINE37655100.00
ROUTINE40900
ROUTINE4091010100.00
ROUTINE47800
ROUTINE47844100.00
ROUTINE49200
ROUTINE49233100.00
ROUTINE54733100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/keccak_2share.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/keccak_2share.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
86 1 1
87 1 1
88 1 1
89 1 1
91 unreachable
98 1 1
99 1 1
114 1 1
115 1 1
116 1 1
125 1 1
129 1 1
136 1 1
143 1 1
296 1 1
297 1 1
314 1 1
315 1 1
322 1 1
324 24 24
344 1 1
363 1 1
364 1 1
365 1 1
366 1 1
370 1 1
376 1 1
377 1 1
378 1 1
379 1 1
383 1 1
409 1 1
410 1 1
412 1 1
413 1 1
415 1 1
416 1 1
419 1 1
420 1 1
421 1 1
424 1 1
478 1 1
479 1 1
480 1 1
483 1 1
492 1 1
493 1 1
495 1 1
547 1 1
548 1 1
550 1 1


Cond Coverage for Module : keccak_2share
TotalCoveredPercent
Conditions8675.00
Logical8675.00
Non-Logical00
Event00

 LINE       415
 EXPRESSION ((z == 0) ? ((W - 1)) : ((z - 1)))
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       415
 SUB-EXPRESSION (z == 0)
                ----1---
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       416
 EXPRESSION (c[ThetaIndexX1[x]][z] ^ c[ThetaIndexX2[x]][index_z])
             ----------1----------   -------------2-------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Module : keccak_2share
Line No.TotalCoveredPercent
Branches 2 1 50.00
TERNARY 415 2 1 50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/keccak_2share.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/keccak_2share.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 415 ((z == 0)) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


Assert Coverage for Module : keccak_2share
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
ValidL_A 1024 1024 0 0
ValidRound_A 1024 1024 0 0
ValidW_A 1024 1024 0 0
ValidWidth_A 1024 1024 0 0


ValidL_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1024 1024 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

ValidRound_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1024 1024 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

ValidW_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1024 1024 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

ValidWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1024 1024 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%