Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	3247	0	0
entropy_period_rd_A	2147483647	1665	0	0
intr_enable_rd_A	2147483647	2065	0	0
prefix_0_rd_A	2147483647	1364	0	0
prefix_10_rd_A	2147483647	1409	0	0
prefix_1_rd_A	2147483647	1382	0	0
prefix_2_rd_A	2147483647	1437	0	0
prefix_3_rd_A	2147483647	1334	0	0
prefix_4_rd_A	2147483647	1355	0	0
prefix_5_rd_A	2147483647	1405	0	0
prefix_6_rd_A	2147483647	1321	0	0
prefix_7_rd_A	2147483647	1376	0	0
prefix_8_rd_A	2147483647	1372	0	0
prefix_9_rd_A	2147483647	1339	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3247	0	0
T50	3347	166	0	0
T52	10308	284	0	0
T115	10148	1	0	0
T118	23160	4	0	0
T119	8745	3	0	0
T120	10369	164	0	0
T133	2262	14	0	0
T137	23321	2	0	0
T138	3734	1	0	0
T140	16756	1	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1665	0	0
T51	4254	16	0	0
T95	5527	15	0	0
T99	7662	25	0	0
T100	6673	37	0	0
T118	23160	125	0	0
T140	16756	63	0	0
T152	2209	8	0	0
T153	1750	8	0	0
T154	63229	63	0	0
T155	1728	6	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2065	0	0
T51	4254	14	0	0
T95	5527	19	0	0
T99	7662	23	0	0
T100	6673	61	0	0
T118	23160	159	0	0
T140	16756	75	0	0
T152	2209	8	0	0
T153	1750	4	0	0
T154	63229	136	0	0
T155	1728	2	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1364	0	0
T51	4254	2	0	0
T95	5527	18	0	0
T99	7662	24	0	0
T100	6673	23	0	0
T118	23160	95	0	0
T140	16756	40	0	0
T152	2209	2	0	0
T153	1750	2	0	0
T154	63229	133	0	0
T155	1728	6	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1409	0	0
T51	4254	7	0	0
T95	5527	13	0	0
T99	7662	11	0	0
T100	6673	34	0	0
T118	23160	79	0	0
T140	16756	54	0	0
T152	2209	4	0	0
T153	1750	1	0	0
T154	63229	123	0	0
T155	1728	2	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1382	0	0
T51	4254	10	0	0
T95	5527	19	0	0
T99	7662	27	0	0
T100	6673	35	0	0
T118	23160	86	0	0
T140	16756	39	0	0
T152	2209	1	0	0
T153	1750	5	0	0
T154	63229	48	0	0
T155	1728	9	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1437	0	0
T51	4254	1	0	0
T95	5527	18	0	0
T99	7662	15	0	0
T100	6673	27	0	0
T118	23160	56	0	0
T140	16756	53	0	0
T152	2209	4	0	0
T153	1750	3	0	0
T154	63229	184	0	0
T156	1923	2	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1334	0	0
T51	4254	17	0	0
T95	5527	28	0	0
T99	7662	18	0	0
T100	6673	25	0	0
T118	23160	87	0	0
T140	16756	48	0	0
T152	2209	4	0	0
T153	1750	3	0	0
T154	63229	117	0	0
T155	1728	3	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1355	0	0
T51	4254	8	0	0
T95	5527	14	0	0
T99	7662	24	0	0
T100	6673	26	0	0
T118	23160	68	0	0
T140	16756	42	0	0
T152	2209	6	0	0
T154	63229	145	0	0
T155	1728	10	0	0
T156	1923	3	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1405	0	0
T51	4254	9	0	0
T52	10308	3	0	0
T95	5527	25	0	0
T99	7662	15	0	0
T100	6673	39	0	0
T118	23160	61	0	0
T152	2209	6	0	0
T153	1750	3	0	0
T154	63229	156	0	0
T155	1728	4	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1321	0	0
T51	4254	13	0	0
T95	5527	17	0	0
T99	7662	25	0	0
T100	6673	21	0	0
T118	23160	61	0	0
T140	16756	33	0	0
T153	1750	1	0	0
T154	63229	106	0	0
T155	1728	5	0	0
T156	1923	5	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1376	0	0
T51	4254	9	0	0
T95	5527	19	0	0
T99	7662	22	0	0
T100	6673	24	0	0
T118	23160	75	0	0
T140	16756	31	0	0
T152	2209	4	0	0
T153	1750	3	0	0
T154	63229	154	0	0
T155	1728	6	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1372	0	0
T51	4254	6	0	0
T95	5527	11	0	0
T99	7662	24	0	0
T100	6673	34	0	0
T118	23160	87	0	0
T140	16756	34	0	0
T152	2209	8	0	0
T153	1750	3	0	0
T154	63229	129	0	0
T155	1728	5	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1339	0	0
T51	4254	15	0	0
T95	5527	16	0	0
T99	7662	28	0	0
T100	6673	25	0	0
T118	23160	59	0	0
T140	16756	41	0	0
T153	1750	5	0	0
T154	63229	108	0	0
T155	1728	7	0	0
T156	1923	4	0	0