Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	258655551	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

203638434

1

T1

261777

T2

100222

T3

359273

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	243806661	1			T1	76237		T2	127400		T3	458743
values[0x0]	105030950	1			T1	102514		T2	551853		T3	212130
values[0x1]	113456374	1			T1	102115		T2	598271		T3	227732

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	201704129	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

260589856

1

T1

266868

T2

131520

T3

475468

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1318069	1			T1	1109		T2	9860		T3	3670
valid_sources[0x01]	1305186	1			T1	1193		T2	9022		T3	3591
valid_sources[0x02]	1316705	1			T1	1066		T2	9139		T3	3509
valid_sources[0x03]	1320795	1			T1	1164		T2	8969		T3	3543
valid_sources[0x04]	1319878	1			T1	1153		T2	8877		T3	3491
valid_sources[0x05]	1380034	1			T1	1124		T2	9308		T3	3690
valid_sources[0x06]	1525817	1			T1	1142		T2	9228		T3	3546
valid_sources[0x07]	3371204	1			T1	1189		T2	9108		T3	3722
valid_sources[0x08]	1316778	1			T1	1105		T2	9145		T3	3631
valid_sources[0x09]	1971701	1			T1	1116		T2	9339		T3	3707
valid_sources[0x0a]	3367155	1			T1	1085		T2	9227		T3	3598
valid_sources[0x0b]	2602946	1			T1	1013		T2	9524		T3	3513
valid_sources[0x0c]	1317066	1			T1	1161		T2	9415		T3	3436
valid_sources[0x0d]	1359818	1			T1	1000		T2	9206		T3	3591
valid_sources[0x0e]	1351972	1			T1	1122		T2	9197		T3	3508
valid_sources[0x0f]	2241106	1			T1	1101		T2	9542		T3	3428
valid_sources[0x10]	1341186	1			T1	1121		T2	9811		T3	3519
valid_sources[0x11]	3386041	1			T1	1046		T2	9230		T3	3626
valid_sources[0x12]	1318024	1			T1	1158		T2	9307		T3	3523
valid_sources[0x13]	1480771	1			T1	1090		T2	9931		T3	3574
valid_sources[0x14]	1322848	1			T1	1057		T2	9503		T3	3486
valid_sources[0x15]	2368304	1			T1	963		T2	9354		T3	3628
valid_sources[0x16]	1450704	1			T1	1181		T2	9481		T3	3422
valid_sources[0x17]	3376276	1			T1	1131		T2	9017		T3	3510
valid_sources[0x18]	1308763	1			T1	1104		T2	9522		T3	3382
valid_sources[0x19]	1317780	1			T1	1146		T2	9629		T3	3552
valid_sources[0x1a]	3803798	1			T1	1183		T2	9403		T3	3405
valid_sources[0x1b]	1323579	1			T1	1129		T2	9261		T3	3427
valid_sources[0x1c]	1316519	1			T1	1115		T2	9152		T3	3510
valid_sources[0x1d]	2439787	1			T1	983		T2	9508		T3	3413
valid_sources[0x1e]	1317913	1			T1	1059		T2	9741		T3	3565
valid_sources[0x1f]	1313353	1			T1	1078		T2	9441		T3	3628
valid_sources[0x20]	1312495	1			T1	1130		T2	9928		T3	3490
valid_sources[0x21]	1321801	1			T1	1117		T2	9535		T3	3588
valid_sources[0x22]	1325870	1			T1	1054		T2	9200		T3	3353
valid_sources[0x23]	1317428	1			T1	1306		T2	8995		T3	3517
valid_sources[0x24]	1322206	1			T1	1124		T2	9349		T3	3456
valid_sources[0x25]	1321720	1			T1	1069		T2	9449		T3	3551
valid_sources[0x26]	3349839	1			T1	1073		T2	9568		T3	3328
valid_sources[0x27]	1330825	1			T1	1083		T2	9550		T3	3656
valid_sources[0x28]	1451830	1			T1	1001		T2	9414		T3	3562
valid_sources[0x29]	2248338	1			T1	1100		T2	9342		T3	3308
valid_sources[0x2a]	1347512	1			T1	852		T2	9211		T3	3279
valid_sources[0x2b]	3586413	1			T1	1061		T2	9435		T3	3519
valid_sources[0x2c]	1655359	1			T1	1011		T2	9036		T3	3407
valid_sources[0x2d]	1314162	1			T1	1161		T2	9161		T3	3717
valid_sources[0x2e]	1317744	1			T1	1050		T2	9771		T3	3529
valid_sources[0x2f]	1964004	1			T1	1169		T2	9573		T3	3511
valid_sources[0x30]	2310232	1			T1	1145		T2	9651		T3	3475
valid_sources[0x31]	1325867	1			T1	1164		T2	9845		T3	3567
valid_sources[0x32]	2224097	1			T1	1038		T2	8783		T3	3446
valid_sources[0x33]	1314774	1			T1	1135		T2	9669		T3	3615
valid_sources[0x34]	1317050	1			T1	1135		T2	9402		T3	3642
valid_sources[0x35]	1312005	1			T1	939		T2	9123		T3	3477
valid_sources[0x36]	1322547	1			T1	1270		T2	9355		T3	3696
valid_sources[0x37]	1313395	1			T1	1147		T2	10069		T3	3632
valid_sources[0x38]	2173906	1			T1	918		T2	9113		T3	3428
valid_sources[0x39]	1321359	1			T1	1208		T2	10111		T3	3452
valid_sources[0x3a]	2414581	1			T1	1018		T2	9398		T3	3361
valid_sources[0x3b]	2224345	1			T1	1047		T2	9081		T3	3563
valid_sources[0x3c]	1317613	1			T1	1139		T2	9258		T3	3500
valid_sources[0x3d]	1339269	1			T1	1199		T2	9848		T3	3745
valid_sources[0x3e]	1317160	1			T1	1300		T2	9306		T3	3773
valid_sources[0x3f]	1311019	1			T1	1126		T2	9682		T3	3313
valid_sources[0x40]	1971352	1			T1	1147		T2	9401		T3	3593
valid_sources[0x41]	1317149	1			T1	1099		T2	9353		T3	3391
valid_sources[0x42]	2985251	1			T1	1161		T2	9288		T3	3641
valid_sources[0x43]	1976191	1			T1	1097		T2	9195		T3	3354
valid_sources[0x44]	1316795	1			T1	1085		T2	10188		T3	3387
valid_sources[0x45]	1604817	1			T1	1039		T2	10063		T3	3497
valid_sources[0x46]	3843675	1			T1	1089		T2	8964		T3	3467
valid_sources[0x47]	2194451	1			T1	1121		T2	8809		T3	3507
valid_sources[0x48]	3741386	1			T1	1145		T2	9425		T3	3480
valid_sources[0x49]	2157885	1			T1	1029		T2	9673		T3	3642
valid_sources[0x4a]	2090492	1			T1	1232		T2	9253		T3	3555
valid_sources[0x4b]	2180297	1			T1	944		T2	9408		T3	3668
valid_sources[0x4c]	1321534	1			T1	1107		T2	9397		T3	3348
valid_sources[0x4d]	2175284	1			T1	1062		T2	9803		T3	3610
valid_sources[0x4e]	1310053	1			T1	1186		T2	9823		T3	3514
valid_sources[0x4f]	1392949	1			T1	1134		T2	9271		T3	3187
valid_sources[0x50]	1965597	1			T1	1115		T2	8983		T3	3528
valid_sources[0x51]	1316632	1			T1	1044		T2	9016		T3	3579
valid_sources[0x52]	2174074	1			T1	936		T2	9940		T3	3559
valid_sources[0x53]	1315252	1			T1	1085		T2	9053		T3	3427
valid_sources[0x54]	1663428	1			T1	1048		T2	9551		T3	3420
valid_sources[0x55]	1496412	1			T1	1006		T2	10083		T3	3566
valid_sources[0x56]	1318224	1			T1	1191		T2	9785		T3	3490
valid_sources[0x57]	2192651	1			T1	1153		T2	9460		T3	3547
valid_sources[0x58]	1319070	1			T1	1041		T2	10187		T3	3569
valid_sources[0x59]	1320014	1			T1	1130		T2	9758		T3	3514
valid_sources[0x5a]	1773504	1			T1	1089		T2	9555		T3	3459
valid_sources[0x5b]	1317955	1			T1	1115		T2	8931		T3	3582
valid_sources[0x5c]	1318225	1			T1	1025		T2	9598		T3	3539
valid_sources[0x5d]	1311307	1			T1	1080		T2	8306		T3	3555
valid_sources[0x5e]	1314502	1			T1	1093		T2	9529		T3	3496
valid_sources[0x5f]	3576888	1			T1	1110		T2	9860		T3	3497
valid_sources[0x60]	2166782	1			T1	1290		T2	9286		T3	3541
valid_sources[0x61]	2035720	1			T1	975		T2	9617		T3	3459
valid_sources[0x62]	3345767	1			T1	1105		T2	9720		T3	3403
valid_sources[0x63]	1341821	1			T1	1202		T2	8881		T3	3652
valid_sources[0x64]	1430548	1			T1	1014		T2	8988		T3	3316
valid_sources[0x65]	1319125	1			T1	1088		T2	9973		T3	3517
valid_sources[0x66]	1317559	1			T1	1124		T2	9553		T3	3363
valid_sources[0x67]	1314435	1			T1	1100		T2	9220		T3	3471
valid_sources[0x68]	1318019	1			T1	950		T2	9481		T3	3482
valid_sources[0x69]	2443571	1			T1	1145		T2	10485		T3	3506
valid_sources[0x6a]	1319344	1			T1	1046		T2	9773		T3	3355
valid_sources[0x6b]	3390600	1			T1	1057		T2	9217		T3	3579
valid_sources[0x6c]	1314550	1			T1	1056		T2	9827		T3	3561
valid_sources[0x6d]	1308455	1			T1	1104		T2	10028		T3	3536
valid_sources[0x6e]	1315365	1			T1	1053		T2	9016		T3	3373
valid_sources[0x6f]	1316799	1			T1	1177		T2	9094		T3	3677
valid_sources[0x70]	1317704	1			T1	1211		T2	9338		T3	3601
valid_sources[0x71]	1319659	1			T1	1165		T2	9283		T3	3540
valid_sources[0x72]	1364399	1			T1	1102		T2	9206		T3	3410
valid_sources[0x73]	1317794	1			T1	1027		T2	9830		T3	3572
valid_sources[0x74]	1318861	1			T1	1144		T2	9023		T3	3542
valid_sources[0x75]	1923127	1			T1	1093		T2	9975		T3	3417
valid_sources[0x76]	1315341	1			T1	1110		T2	9549		T3	3711
valid_sources[0x77]	1601924	1			T1	971		T2	9927		T3	3377
valid_sources[0x78]	1313641	1			T1	1139		T2	9317		T3	3373
valid_sources[0x79]	1315166	1			T1	1171		T2	9283		T3	3614
valid_sources[0x7a]	3335197	1			T1	1124		T2	9515		T3	3591
valid_sources[0x7b]	1470575	1			T1	1080		T2	9485		T3	3499
valid_sources[0x7c]	1332434	1			T1	1329		T2	9491		T3	3484
valid_sources[0x7d]	1317462	1			T1	889		T2	9859		T3	3362
valid_sources[0x7e]	1775732	1			T1	1153		T2	9848		T3	3644
valid_sources[0x7f]	1317013	1			T1	1234		T2	9915		T3	3402
valid_sources[0x80]	1307090	1			T1	1065		T2	9466		T3	3299

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

88592712

1

T1

60079

T2

427431

T3

131298

values[0x0]

all_enables

biggest_size

61881380

1

T1

101213

T2

311669

T3

123415

values[0x1]

all_enables

biggest_size

53164342

1

T1

100485

T2

263121

T3

104560