Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

259066852

1

T1

19089

T2

142190

T3

539332

full_word

203663925

1

T1

261777

T2

100222

T3

359273

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	462730467	1			T1	280866		T2	242412		T3	898605
auto[TlIntgErrCmd]	98	1			T105	11		T106	3		T107	2
auto[TlIntgErrData]	115	1			T105	5		T106	9		T107	3
auto[TlIntgErrBoth]	97	1			T105	4		T106	8		T107	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

243884727

1

T1

76237

T2

127400

T3

458743

auto[1]

218846050

1

T1

204629

T2

115012

T3

439862

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	155285450	1			T1	16158		T2	846573		T3	327445
auto[TlIntgErrNone]	partial	auto[1]	103781112	1			T1	2931		T2	575334		T3	211887
auto[TlIntgErrNone]	full_word	auto[0]	88599126	1			T1	60079		T2	427431		T3	131298
auto[TlIntgErrNone]	full_word	auto[1]	115064779	1			T1	201698		T2	574790		T3	227975
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T105	6		T106	2		T107	2
auto[TlIntgErrCmd]	partial	auto[1]	49	1			T105	4		T106	1		T120	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T167	1		T168	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T105	1		T120	1		T130	1
auto[TlIntgErrData]	partial	auto[0]	53	1			T105	2		T106	5		T107	1
auto[TlIntgErrData]	partial	auto[1]	54	1			T105	3		T106	4		T107	2
auto[TlIntgErrData]	full_word	auto[0]	4	1			T131	1		T167	1		T169	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T120	2		T165	1		T170	1
auto[TlIntgErrBoth]	partial	auto[0]	45	1			T105	3		T106	6		T107	2
auto[TlIntgErrBoth]	partial	auto[1]	46	1			T105	1		T106	2		T107	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T107	1		T120	1		T171	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T131	1		T168	1		-	-