Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	97025	0	0
entropy_period_rd_A	2147483647	2129	0	0
intr_enable_rd_A	2147483647	2755	0	0
prefix_0_rd_A	2147483647	2059	0	0
prefix_10_rd_A	2147483647	2035	0	0
prefix_1_rd_A	2147483647	2138	0	0
prefix_2_rd_A	2147483647	1953	0	0
prefix_3_rd_A	2147483647	2158	0	0
prefix_4_rd_A	2147483647	2125	0	0
prefix_5_rd_A	2147483647	2053	0	0
prefix_6_rd_A	2147483647	2037	0	0
prefix_7_rd_A	2147483647	2171	0	0
prefix_8_rd_A	2147483647	2176	0	0
prefix_9_rd_A	2147483647	2165	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	97025	0	0
T51	674483	94020	0	0
T52	0	4	0	0
T53	0	1	0	0
T105	0	3	0	0
T106	0	2	0	0
T108	0	72	0	0
T109	0	108	0	0
T116	0	132	0	0
T118	0	3	0	0
T119	0	3	0	0
T121	454760	0	0	0
T122	186435	0	0	0
T123	145197	0	0	0
T124	257333	0	0	0
T125	259281	0	0	0
T126	5796	0	0	0
T127	134262	0	0	0
T128	825123	0	0	0
T129	8060	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2129	0	0
T52	8322	20	0	0
T91	6114	42	0	0
T105	22312	97	0	0
T118	4608	9	0	0
T120	27460	116	0	0
T130	22984	70	0	0
T131	20976	51	0	0
T142	9932	48	0	0
T143	1810	4	0	0
T144	72607	123	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2755	0	0
T52	8322	26	0	0
T91	6114	52	0	0
T105	22312	167	0	0
T111	756	8	0	0
T112	1045	19	0	0
T118	4608	7	0	0
T120	27460	147	0	0
T142	9932	5	0	0
T145	866	19	0	0
T146	1072	30	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2059	0	0
T52	8322	13	0	0
T91	6114	20	0	0
T93	3413	10	0	0
T105	22312	57	0	0
T118	4608	2	0	0
T120	27460	101	0	0
T130	22984	76	0	0
T131	20976	24	0	0
T142	9932	19	0	0
T143	1810	6	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2035	0	0
T52	8322	10	0	0
T91	6114	22	0	0
T105	22312	81	0	0
T118	4608	10	0	0
T120	27460	90	0	0
T130	22984	45	0	0
T131	20976	23	0	0
T142	9932	14	0	0
T143	1810	6	0	0
T144	72607	225	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2138	0	0
T52	8322	9	0	0
T91	6114	39	0	0
T93	3413	6	0	0
T105	22312	70	0	0
T118	4608	3	0	0
T120	27460	78	0	0
T130	22984	60	0	0
T131	20976	42	0	0
T142	9932	7	0	0
T143	1810	1	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1953	0	0
T52	8322	3	0	0
T91	6114	29	0	0
T93	3413	3	0	0
T105	22312	87	0	0
T118	4608	4	0	0
T120	27460	70	0	0
T130	22984	57	0	0
T131	20976	52	0	0
T142	9932	5	0	0
T143	1810	6	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2158	0	0
T52	8322	16	0	0
T91	6114	33	0	0
T93	3413	9	0	0
T105	22312	68	0	0
T108	6690	1	0	0
T118	4608	9	0	0
T120	27460	84	0	0
T130	22984	49	0	0
T131	20976	55	0	0
T142	9932	30	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2125	0	0
T52	8322	11	0	0
T91	6114	32	0	0
T93	3413	4	0	0
T105	22312	87	0	0
T118	4608	7	0	0
T120	27460	96	0	0
T130	22984	46	0	0
T131	20976	38	0	0
T142	9932	38	0	0
T143	1810	5	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2053	0	0
T52	8322	22	0	0
T91	6114	28	0	0
T93	3413	1	0	0
T105	22312	70	0	0
T118	4608	12	0	0
T120	27460	93	0	0
T130	22984	43	0	0
T131	20976	29	0	0
T142	9932	20	0	0
T144	72607	226	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2037	0	0
T52	8322	13	0	0
T91	6114	17	0	0
T93	3413	5	0	0
T105	22312	112	0	0
T118	4608	13	0	0
T120	27460	78	0	0
T130	22984	27	0	0
T131	20976	38	0	0
T142	9932	24	0	0
T143	1810	2	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2171	0	0
T52	8322	14	0	0
T91	6114	33	0	0
T105	22312	97	0	0
T118	4608	14	0	0
T120	27460	91	0	0
T130	22984	30	0	0
T131	20976	63	0	0
T142	9932	40	0	0
T143	1810	1	0	0
T144	72607	236	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2176	0	0
T52	8322	16	0	0
T91	6114	33	0	0
T93	3413	10	0	0
T105	22312	88	0	0
T118	4608	7	0	0
T120	27460	88	0	0
T130	22984	47	0	0
T131	20976	50	0	0
T142	9932	45	0	0
T143	1810	5	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2165	0	0
T52	8322	24	0	0
T91	6114	37	0	0
T93	3413	4	0	0
T105	22312	85	0	0
T118	4608	4	0	0
T120	27460	88	0	0
T130	22984	72	0	0
T131	20976	31	0	0
T142	9932	10	0	0
T143	1810	4	0	0