Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

252745923

1

T1

23

T2

243843

T3

50991

full_word

197991348

1

T1

176

T2

176550

T3

89741

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	450736971	1			T1	199		T2	420393		T3	140732
auto[TlIntgErrCmd]	90	1			T109	3		T110	2		T111	3
auto[TlIntgErrData]	100	1			T109	5		T110	5		T111	3
auto[TlIntgErrBoth]	110	1			T109	2		T110	3		T111	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

237750241

1

T1

66

T2

224462

T3

100238

auto[1]

212987030

1

T1

133

T2

195931

T3

40494

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	151652622	1			T1	12		T2	148134		T3	32677
auto[TlIntgErrNone]	partial	auto[1]	101093027	1			T1	11		T2	95709		T3	18314
auto[TlIntgErrNone]	full_word	auto[0]	86097471	1			T1	54		T2	76328		T3	67561
auto[TlIntgErrNone]	full_word	auto[1]	111893851	1			T1	122		T2	100222		T3	22180
auto[TlIntgErrCmd]	partial	auto[0]	46	1			T109	2		T110	1		T133	6
auto[TlIntgErrCmd]	partial	auto[1]	39	1			T109	1		T110	1		T111	3
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T176	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T134	1		T177	1		T178	1
auto[TlIntgErrData]	partial	auto[0]	44	1			T109	2		T110	3		T111	1
auto[TlIntgErrData]	partial	auto[1]	43	1			T109	2		T110	2		T111	2
auto[TlIntgErrData]	full_word	auto[0]	8	1			T109	1		T133	1		T179	2
auto[TlIntgErrData]	full_word	auto[1]	5	1			T180	1		T177	1		T181	1
auto[TlIntgErrBoth]	partial	auto[0]	44	1			T111	2		T133	2		T134	1
auto[TlIntgErrBoth]	partial	auto[1]	58	1			T109	2		T110	3		T111	2
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T179	1		T181	1		T178	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T134	1		T179	1		T182	1