Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	251492116	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

197507708

1

T1

354

T2

8548

T3

1409

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	237272814	1			T1	64		T2	9480		T3	1131
values[0x0]	101776198	1			T1	178		T2	1817		T3	493
values[0x1]	109950812	1			T1	189		T2	1932		T3	551

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	196126219	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

252873605

1

T1

369

T2

9588

T3

1567

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3799093	1			T1	16		T2	68		T3	2
valid_sources[0x01]	1391790	1			T1	2		T2	39		T3	19
valid_sources[0x02]	1399559	1			T1	2		T2	51		T3	17
valid_sources[0x03]	1397531	1			T2	61		T3	2		T13	4
valid_sources[0x04]	1399314	1			T1	2		T2	47		T3	5
valid_sources[0x05]	1482648	1			T2	50		T3	4		T13	7
valid_sources[0x06]	1392824	1			T1	2		T2	69		T3	14
valid_sources[0x07]	1394758	1			T1	1		T2	55		T3	18
valid_sources[0x08]	2070508	1			T1	1		T2	66		T3	2
valid_sources[0x09]	5202719	1			T1	4		T2	35		T3	13
valid_sources[0x0a]	1396989	1			T2	45		T3	4		T13	9
valid_sources[0x0b]	2306535	1			T1	7		T2	37		T3	19
valid_sources[0x0c]	1570862	1			T2	59		T3	18		T13	3
valid_sources[0x0d]	1390915	1			T1	3		T2	56		T3	5
valid_sources[0x0e]	1753160	1			T2	42		T3	8		T13	7
valid_sources[0x0f]	2281486	1			T2	59		T3	11		T13	7
valid_sources[0x10]	1394697	1			T1	4		T2	52		T3	15
valid_sources[0x11]	1406307	1			T2	43		T3	8		T13	2
valid_sources[0x12]	1494393	1			T2	46		T3	12		T13	5
valid_sources[0x13]	1396715	1			T2	51		T3	9		T13	20
valid_sources[0x14]	2313682	1			T2	31		T3	13		T13	6
valid_sources[0x15]	1392405	1			T1	6		T2	47		T3	9
valid_sources[0x16]	1421436	1			T2	49		T3	6		T13	2
valid_sources[0x17]	3830043	1			T2	78		T3	7		T13	7
valid_sources[0x18]	1425889	1			T1	2		T2	34		T3	4
valid_sources[0x19]	1399022	1			T1	1		T2	36		T3	5
valid_sources[0x1a]	1434466	1			T2	25		T3	8		T13	4
valid_sources[0x1b]	1391645	1			T2	47		T3	1		T13	9
valid_sources[0x1c]	1391618	1			T1	3		T2	33		T3	15
valid_sources[0x1d]	3840206	1			T2	59		T3	6		T13	8
valid_sources[0x1e]	2236383	1			T1	1		T2	56		T13	12
valid_sources[0x1f]	1403975	1			T1	2		T2	54		T3	5
valid_sources[0x20]	1392748	1			T2	48		T3	8		T13	13
valid_sources[0x21]	2072227	1			T2	60		T3	4		T13	6
valid_sources[0x22]	1394609	1			T2	46		T3	7		T13	4
valid_sources[0x23]	1495897	1			T2	50		T3	13		T13	5
valid_sources[0x24]	1423654	1			T2	46		T3	7		T13	3
valid_sources[0x25]	1395411	1			T1	10		T2	33		T3	3
valid_sources[0x26]	2362323	1			T2	53		T3	13		T13	4
valid_sources[0x27]	1382799	1			T1	2		T2	31		T3	12
valid_sources[0x28]	1393865	1			T1	2		T2	69		T3	5
valid_sources[0x29]	2201058	1			T2	49		T3	17		T13	2
valid_sources[0x2a]	1393778	1			T1	3		T2	70		T3	4
valid_sources[0x2b]	1396687	1			T1	1		T2	51		T3	9
valid_sources[0x2c]	2253429	1			T1	2		T2	47		T3	16
valid_sources[0x2d]	1403503	1			T1	1		T2	48		T3	3
valid_sources[0x2e]	1562213	1			T1	2		T2	41		T3	14
valid_sources[0x2f]	1393065	1			T1	1		T2	39		T3	12
valid_sources[0x30]	1394154	1			T1	2		T2	61		T3	10
valid_sources[0x31]	1393477	1			T1	2		T2	50		T3	6
valid_sources[0x32]	1386197	1			T1	2		T2	46		T3	12
valid_sources[0x33]	4806200	1			T2	65		T3	4		T13	4
valid_sources[0x34]	3577288	1			T1	4		T2	51		T3	17
valid_sources[0x35]	2312064	1			T2	34		T3	3		T13	12
valid_sources[0x36]	1390919	1			T1	1		T2	57		T3	8
valid_sources[0x37]	1387352	1			T2	56		T3	7		T13	1
valid_sources[0x38]	1553379	1			T1	5		T2	38		T3	3
valid_sources[0x39]	1398413	1			T2	63		T3	1		T13	6
valid_sources[0x3a]	2279818	1			T2	43		T3	11		T13	14
valid_sources[0x3b]	1400743	1			T1	4		T2	24		T3	10
valid_sources[0x3c]	1390342	1			T2	37		T3	5		T13	6
valid_sources[0x3d]	1402624	1			T1	3		T2	65		T3	2
valid_sources[0x3e]	1398945	1			T1	10		T2	46		T3	5
valid_sources[0x3f]	1397950	1			T1	2		T2	41		T3	2
valid_sources[0x40]	1402809	1			T1	3		T2	54		T3	9
valid_sources[0x41]	1396875	1			T2	53		T3	14		T13	5
valid_sources[0x42]	1390049	1			T1	7		T2	47		T3	9
valid_sources[0x43]	1387450	1			T2	68		T3	8		T13	3
valid_sources[0x44]	1396827	1			T2	53		T3	10		T13	12
valid_sources[0x45]	1392327	1			T2	49		T3	5		T13	3
valid_sources[0x46]	3444936	1			T1	4		T2	39		T3	5
valid_sources[0x47]	1567806	1			T2	67		T3	6		T13	10
valid_sources[0x48]	1390656	1			T2	48		T3	24		T13	12
valid_sources[0x49]	1395915	1			T1	6		T2	37		T3	5
valid_sources[0x4a]	1434203	1			T1	7		T2	51		T3	5
valid_sources[0x4b]	3206852	1			T2	53		T3	11		T13	8
valid_sources[0x4c]	1525856	1			T1	1		T2	53		T3	9
valid_sources[0x4d]	1872654	1			T1	1		T2	53		T3	6
valid_sources[0x4e]	1393588	1			T2	55		T3	12		T13	7
valid_sources[0x4f]	1394782	1			T1	1		T2	61		T3	8
valid_sources[0x50]	1397274	1			T2	32		T3	5		T13	3
valid_sources[0x51]	1516771	1			T2	77		T13	19		T14	15
valid_sources[0x52]	1399926	1			T2	61		T3	6		T13	2
valid_sources[0x53]	1850612	1			T1	1		T2	58		T3	4
valid_sources[0x54]	3855177	1			T1	4		T2	55		T3	5
valid_sources[0x55]	1398671	1			T2	47		T3	9		T13	8
valid_sources[0x56]	1517323	1			T1	1		T2	49		T3	8
valid_sources[0x57]	1401357	1			T2	69		T3	9		T13	3
valid_sources[0x58]	3961654	1			T1	11		T2	47		T3	4
valid_sources[0x59]	1387808	1			T2	51		T3	6		T13	3
valid_sources[0x5a]	1400284	1			T1	2		T2	52		T3	5
valid_sources[0x5b]	1391044	1			T1	4		T2	24		T3	24
valid_sources[0x5c]	1391155	1			T1	1		T2	59		T3	9
valid_sources[0x5d]	1531316	1			T1	6		T2	53		T3	10
valid_sources[0x5e]	1426031	1			T2	41		T3	10		T13	3
valid_sources[0x5f]	2076413	1			T1	3		T2	55		T3	5
valid_sources[0x60]	1422242	1			T1	2		T2	61		T3	7
valid_sources[0x61]	2314594	1			T2	54		T3	17		T13	7
valid_sources[0x62]	1391084	1			T2	39		T3	10		T13	2
valid_sources[0x63]	1395347	1			T2	19		T3	7		T13	8
valid_sources[0x64]	1399226	1			T1	3		T2	51		T3	9
valid_sources[0x65]	2568760	1			T2	37		T3	2		T13	4
valid_sources[0x66]	1397440	1			T1	4		T2	36		T3	13
valid_sources[0x67]	1394219	1			T1	3		T2	63		T3	12
valid_sources[0x68]	1388496	1			T2	62		T3	10		T13	5
valid_sources[0x69]	1401139	1			T1	1		T2	58		T3	4
valid_sources[0x6a]	2309112	1			T1	4		T2	44		T3	10
valid_sources[0x6b]	1396651	1			T2	57		T3	17		T13	7
valid_sources[0x6c]	1395275	1			T2	40		T3	6		T13	12
valid_sources[0x6d]	1466709	1			T1	9		T2	57		T3	6
valid_sources[0x6e]	3828345	1			T1	7		T2	44		T3	10
valid_sources[0x6f]	1394750	1			T2	54		T3	11		T13	3
valid_sources[0x70]	1389250	1			T2	52		T3	4		T13	6
valid_sources[0x71]	1394548	1			T2	53		T3	15		T13	6
valid_sources[0x72]	1397309	1			T1	2		T2	56		T3	10
valid_sources[0x73]	1389182	1			T2	44		T3	18		T13	12
valid_sources[0x74]	2371140	1			T2	50		T3	6		T13	4
valid_sources[0x75]	3455956	1			T2	74		T3	13		T13	2
valid_sources[0x76]	1504246	1			T1	4		T2	49		T3	5
valid_sources[0x77]	1398134	1			T1	2		T2	36		T3	8
valid_sources[0x78]	1394585	1			T2	41		T3	7		T14	14
valid_sources[0x79]	1388725	1			T1	1		T2	34		T3	12
valid_sources[0x7a]	1558339	1			T2	61		T3	5		T13	17
valid_sources[0x7b]	1487740	1			T2	54		T3	2		T13	3
valid_sources[0x7c]	1514140	1			T1	3		T2	68		T3	1
valid_sources[0x7d]	1394290	1			T1	3		T2	55		T3	5
valid_sources[0x7e]	1395610	1			T1	8		T2	52		T3	6
valid_sources[0x7f]	1402507	1			T2	37		T3	6		T13	7
valid_sources[0x80]	1389598	1			T2	59		T3	12		T13	17

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

86410179

1

T1

11

T2

6432

T3

705

values[0x0]

all_enables

biggest_size

59800542

1

T1

169

T2

1142

T3

364

values[0x1]

all_enables

biggest_size

51296987

1

T1

174

T2

974

T3

340