Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

251683321

1

T1

77

T2

4681

T3

766

full_word

197519691

1

T1

354

T2

8548

T3

1409

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	449202752	1			T1	431		T2	13229		T3	2175
auto[TlIntgErrCmd]	82	1			T51	4		T118	4		T119	4
auto[TlIntgErrData]	88	1			T51	4		T118	4		T119	4
auto[TlIntgErrBoth]	90	1			T51	2		T118	12		T119	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

237310360

1

T1

64

T2

9480

T3

1131

auto[1]

211892652

1

T1

367

T2

3749

T3

1044

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	150897102	1			T1	53		T2	3048		T3	426
auto[TlIntgErrNone]	partial	auto[1]	100785986	1			T1	24		T2	1633		T3	340
auto[TlIntgErrNone]	full_word	auto[0]	86413144	1			T1	11		T2	6432		T3	705
auto[TlIntgErrNone]	full_word	auto[1]	111106520	1			T1	343		T2	2116		T3	704
auto[TlIntgErrCmd]	partial	auto[0]	33	1			T51	1		T118	1		T148	3
auto[TlIntgErrCmd]	partial	auto[1]	41	1			T51	3		T118	2		T119	3
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T118	1		T119	1		T148	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T171	1		T170	1		T173	1
auto[TlIntgErrData]	partial	auto[0]	38	1			T51	1		T118	1		T148	4
auto[TlIntgErrData]	partial	auto[1]	42	1			T51	1		T118	3		T119	3
auto[TlIntgErrData]	full_word	auto[0]	3	1			T51	1		T174	1		T175	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T51	1		T119	1		T175	1
auto[TlIntgErrBoth]	partial	auto[0]	31	1			T51	2		T118	3		T148	5
auto[TlIntgErrBoth]	partial	auto[1]	48	1			T118	8		T119	2		T148	5
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T118	1		T148	1		T170	2
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T148	1		T169	1		T171	1