Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	45016	0	0
entropy_period_rd_A	2147483647	2317	0	0
intr_enable_rd_A	2147483647	3200	0	0
prefix_0_rd_A	2147483647	2559	0	0
prefix_10_rd_A	2147483647	2490	0	0
prefix_1_rd_A	2147483647	2564	0	0
prefix_2_rd_A	2147483647	2495	0	0
prefix_3_rd_A	2147483647	2387	0	0
prefix_4_rd_A	2147483647	2502	0	0
prefix_5_rd_A	2147483647	2533	0	0
prefix_6_rd_A	2147483647	2609	0	0
prefix_7_rd_A	2147483647	2685	0	0
prefix_8_rd_A	2147483647	2377	0	0
prefix_9_rd_A	2147483647	2453	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	45016	0	0
T49	163010	15248	0	0
T50	0	26623	0	0
T51	0	1	0	0
T117	0	7	0	0
T118	0	4	0	0
T119	0	1	0	0
T120	0	208	0	0
T121	0	218	0	0
T126	0	177	0	0
T127	0	32	0	0
T129	606413	0	0	0
T130	899926	0	0	0
T131	251574	0	0	0
T132	495344	0	0	0
T133	187740	0	0	0
T134	556289	0	0	0
T135	511480	0	0	0
T136	172599	0	0	0
T137	91530	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2317	0	0
T93	4255	10	0	0
T95	11637	90	0	0
T97	10973	65	0	0
T99	3480	9	0	0
T145	1718	4	0	0
T146	3714	12	0	0
T147	6607	26	0	0
T148	21836	26	0	0
T149	7404	43	0	0
T150	144611	219	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3200	0	0
T93	4255	7	0	0
T95	11637	69	0	0
T97	10973	81	0	0
T122	1353	30	0	0
T123	1419	26	0	0
T124	1316	11	0	0
T145	1718	19	0	0
T146	3714	9	0	0
T147	6607	8	0	0
T148	21836	105	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2559	0	0
T93	4255	10	0	0
T95	11637	52	0	0
T97	10973	51	0	0
T99	3480	3	0	0
T145	1718	1	0	0
T146	3714	13	0	0
T147	6607	4	0	0
T148	21836	52	0	0
T149	7404	39	0	0
T150	144611	505	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2490	0	0
T93	4255	8	0	0
T95	11637	50	0	0
T97	10973	65	0	0
T99	3480	8	0	0
T145	1718	6	0	0
T146	3714	15	0	0
T147	6607	19	0	0
T148	21836	37	0	0
T149	7404	38	0	0
T150	144611	499	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2564	0	0
T93	4255	1	0	0
T95	11637	53	0	0
T97	10973	54	0	0
T99	3480	12	0	0
T145	1718	8	0	0
T146	3714	5	0	0
T147	6607	23	0	0
T148	21836	44	0	0
T149	7404	35	0	0
T150	144611	481	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2495	0	0
T93	4255	1	0	0
T95	11637	52	0	0
T97	10973	67	0	0
T99	3480	7	0	0
T145	1718	8	0	0
T146	3714	15	0	0
T147	6607	27	0	0
T148	21836	24	0	0
T149	7404	35	0	0
T150	144611	397	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2387	0	0
T93	4255	7	0	0
T95	11637	29	0	0
T97	10973	58	0	0
T99	3480	5	0	0
T145	1718	3	0	0
T146	3714	12	0	0
T147	6607	22	0	0
T148	21836	16	0	0
T149	7404	31	0	0
T150	144611	441	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2502	0	0
T95	11637	58	0	0
T97	10973	65	0	0
T145	1718	9	0	0
T146	3714	4	0	0
T147	6607	28	0	0
T148	21836	39	0	0
T149	7404	31	0	0
T150	144611	443	0	0
T151	7140	31	0	0
T152	12246	108	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2533	0	0
T93	4255	6	0	0
T95	11637	42	0	0
T97	10973	46	0	0
T99	3480	4	0	0
T145	1718	1	0	0
T146	3714	4	0	0
T147	6607	40	0	0
T148	21836	61	0	0
T149	7404	34	0	0
T150	144611	447	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2609	0	0
T93	4255	17	0	0
T95	11637	41	0	0
T97	10973	67	0	0
T99	3480	2	0	0
T145	1718	1	0	0
T146	3714	13	0	0
T147	6607	35	0	0
T148	21836	56	0	0
T149	7404	34	0	0
T150	144611	447	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2685	0	0
T95	11637	38	0	0
T97	10973	76	0	0
T99	3480	11	0	0
T146	3714	12	0	0
T147	6607	12	0	0
T148	21836	51	0	0
T149	7404	29	0	0
T150	144611	498	0	0
T151	7140	8	0	0
T152	12246	43	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2377	0	0
T93	4255	8	0	0
T95	11637	44	0	0
T97	10973	63	0	0
T99	3480	10	0	0
T145	1718	2	0	0
T146	3714	5	0	0
T147	6607	9	0	0
T148	21836	40	0	0
T149	7404	23	0	0
T150	144611	473	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2453	0	0
T93	4255	18	0	0
T95	11637	43	0	0
T97	10973	76	0	0
T99	3480	14	0	0
T145	1718	1	0	0
T146	3714	5	0	0
T147	6607	9	0	0
T148	21836	46	0	0
T149	7404	30	0	0
T150	144611	399	0	0