Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	253630946	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

199256289

1

T1

66531

T2

100271

T3

23425

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	239319067	1			T1	74312		T2	126552		T3	25699
values[0x0]	102662368	1			T1	16651		T2	548482		T3	5098
values[0x1]	110905800	1			T1	17644		T2	593152		T3	5415

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	197801729	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

255085506

1

T1

76306

T2

130920

T3

26381

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1427551	1			T1	426		T2	9316		T3	77
valid_sources[0x01]	1554050	1			T1	422		T2	9453		T3	88
valid_sources[0x02]	1501952	1			T1	380		T2	9413		T3	63
valid_sources[0x03]	1358446	1			T1	458		T2	9377		T3	214
valid_sources[0x04]	1488498	1			T1	392		T2	9454		T3	304
valid_sources[0x05]	1372950	1			T1	384		T2	9276		T3	237
valid_sources[0x06]	1518448	1			T1	386		T2	9487		T3	136
valid_sources[0x07]	1548457	1			T1	485		T2	9355		T3	99
valid_sources[0x08]	1837729	1			T1	449		T2	9291		T3	166
valid_sources[0x09]	3810768	1			T1	417		T2	9482		T3	76
valid_sources[0x0a]	1364520	1			T1	459		T2	9572		T3	41
valid_sources[0x0b]	1392337	1			T1	462		T2	9521		T3	45
valid_sources[0x0c]	1556046	1			T1	415		T2	9468		T3	298
valid_sources[0x0d]	1361637	1			T1	351		T2	9445		T3	85
valid_sources[0x0e]	2244930	1			T1	481		T2	9328		T3	164
valid_sources[0x0f]	1368629	1			T1	421		T2	9414		T3	240
valid_sources[0x10]	1360498	1			T1	415		T2	9221		T3	210
valid_sources[0x11]	1363151	1			T1	368		T2	9643		T3	73
valid_sources[0x12]	1418259	1			T1	435		T2	9486		T3	251
valid_sources[0x13]	1366680	1			T1	426		T2	9339		T3	98
valid_sources[0x14]	2511121	1			T1	398		T2	9417		T3	95
valid_sources[0x15]	1361141	1			T1	415		T2	9383		T3	44
valid_sources[0x16]	2140314	1			T1	458		T2	9256		T3	81
valid_sources[0x17]	2866416	1			T1	415		T2	9202		T3	196
valid_sources[0x18]	1359220	1			T1	458		T2	9413		T3	60
valid_sources[0x19]	1373081	1			T1	406		T2	9451		T3	163
valid_sources[0x1a]	1368607	1			T1	434		T2	9251		T3	229
valid_sources[0x1b]	1362696	1			T1	407		T2	9459		T3	57
valid_sources[0x1c]	1360962	1			T1	423		T2	9325		T3	187
valid_sources[0x1d]	1364828	1			T1	404		T2	9393		T3	88
valid_sources[0x1e]	2266727	1			T1	388		T2	9415		T3	114
valid_sources[0x1f]	1364721	1			T1	388		T2	9468		T3	175
valid_sources[0x20]	1357999	1			T1	426		T2	9249		T3	104
valid_sources[0x21]	1371745	1			T1	397		T2	9268		T3	197
valid_sources[0x22]	1512248	1			T1	451		T2	9610		T3	88
valid_sources[0x23]	1533340	1			T1	396		T2	9434		T3	190
valid_sources[0x24]	1373742	1			T1	408		T2	9460		T3	83
valid_sources[0x25]	1822544	1			T1	435		T2	9469		T3	19
valid_sources[0x26]	1597782	1			T1	461		T2	9363		T3	108
valid_sources[0x27]	1407577	1			T1	420		T2	9581		T3	227
valid_sources[0x28]	1425469	1			T1	474		T2	9212		T3	65
valid_sources[0x29]	2067341	1			T1	454		T2	9384		T3	136
valid_sources[0x2a]	1361620	1			T1	459		T2	9522		T3	163
valid_sources[0x2b]	1436144	1			T1	435		T2	9387		T3	187
valid_sources[0x2c]	1362109	1			T1	446		T2	9542		T3	67
valid_sources[0x2d]	1362145	1			T1	409		T2	9522		T3	51
valid_sources[0x2e]	1416240	1			T1	401		T2	9255		T3	71
valid_sources[0x2f]	2711200	1			T1	405		T2	9464		T3	100
valid_sources[0x30]	1365955	1			T1	417		T2	9450		T3	116
valid_sources[0x31]	1466985	1			T1	350		T2	9161		T3	357
valid_sources[0x32]	1811510	1			T1	462		T2	9294		T3	207
valid_sources[0x33]	3896525	1			T1	411		T2	9364		T3	285
valid_sources[0x34]	1363775	1			T1	396		T2	9413		T3	100
valid_sources[0x35]	1359092	1			T1	443		T2	9529		T3	50
valid_sources[0x36]	1388182	1			T1	416		T2	9228		T3	185
valid_sources[0x37]	1370686	1			T1	485		T2	9404		T3	40
valid_sources[0x38]	1365986	1			T1	414		T2	9532		T3	45
valid_sources[0x39]	1365841	1			T1	421		T2	9463		T3	112
valid_sources[0x3a]	1363135	1			T1	422		T2	9432		T3	112
valid_sources[0x3b]	1375197	1			T1	418		T2	9456		T3	378
valid_sources[0x3c]	1368036	1			T1	454		T2	9366		T3	203
valid_sources[0x3d]	1817920	1			T1	405		T2	9391		T3	135
valid_sources[0x3e]	1816112	1			T1	418		T2	9331		T3	191
valid_sources[0x3f]	1357577	1			T1	407		T2	9487		T3	208
valid_sources[0x40]	1359292	1			T1	465		T2	9314		T3	130
valid_sources[0x41]	1539899	1			T1	379		T2	9215		T3	77
valid_sources[0x42]	2298470	1			T1	436		T2	9551		T3	134
valid_sources[0x43]	1359752	1			T1	395		T2	9393		T3	166
valid_sources[0x44]	5647232	1			T1	453		T2	9267		T3	92
valid_sources[0x45]	1421980	1			T1	378		T2	9306		T3	60
valid_sources[0x46]	1416756	1			T1	398		T2	9256		T3	257
valid_sources[0x47]	1368886	1			T1	397		T2	9388		T3	94
valid_sources[0x48]	1369937	1			T1	416		T2	9374		T3	158
valid_sources[0x49]	1770428	1			T1	414		T2	9526		T3	144
valid_sources[0x4a]	2263898	1			T1	462		T2	9527		T3	251
valid_sources[0x4b]	1863698	1			T1	449		T2	9548		T3	71
valid_sources[0x4c]	2301911	1			T1	406		T2	9527		T3	33
valid_sources[0x4d]	1363467	1			T1	462		T2	9451		T3	188
valid_sources[0x4e]	2287036	1			T1	423		T2	9282		T3	86
valid_sources[0x4f]	2220526	1			T1	366		T2	9173		T3	163
valid_sources[0x50]	2280659	1			T1	380		T2	9301		T3	67
valid_sources[0x51]	5345127	1			T1	366		T2	9238		T3	172
valid_sources[0x52]	1369082	1			T1	426		T2	9313		T3	135
valid_sources[0x53]	1355586	1			T1	430		T2	9215		T3	47
valid_sources[0x54]	1378983	1			T1	421		T2	9446		T3	5
valid_sources[0x55]	1514935	1			T1	447		T2	9462		T3	249
valid_sources[0x56]	1369471	1			T1	382		T2	9297		T3	40
valid_sources[0x57]	1867441	1			T1	400		T2	9559		T3	48
valid_sources[0x58]	2215028	1			T1	398		T2	9326		T3	75
valid_sources[0x59]	1826213	1			T1	402		T2	9316		T3	93
valid_sources[0x5a]	1431751	1			T1	400		T2	9273		T3	51
valid_sources[0x5b]	1360680	1			T1	431		T2	9386		T3	328
valid_sources[0x5c]	1426801	1			T1	345		T2	9389		T3	143
valid_sources[0x5d]	1364292	1			T1	406		T2	9274		T3	102
valid_sources[0x5e]	1356948	1			T1	338		T2	9483		T3	113
valid_sources[0x5f]	1362389	1			T1	442		T2	9355		T3	177
valid_sources[0x60]	1370130	1			T1	387		T2	9305		T3	102
valid_sources[0x61]	1365134	1			T1	476		T2	9396		T3	210
valid_sources[0x62]	1379814	1			T1	427		T2	9396		T3	253
valid_sources[0x63]	1363318	1			T1	456		T2	9393		T3	142
valid_sources[0x64]	1366880	1			T1	419		T2	9401		T3	25
valid_sources[0x65]	1411031	1			T1	474		T2	9418		T3	118
valid_sources[0x66]	2034133	1			T1	422		T2	9403		T3	218
valid_sources[0x67]	3425350	1			T1	439		T2	9363		T3	164
valid_sources[0x68]	1558221	1			T1	406		T2	9540		T3	213
valid_sources[0x69]	1362501	1			T1	431		T2	9367		T3	170
valid_sources[0x6a]	2477145	1			T1	411		T2	9559		T3	273
valid_sources[0x6b]	1363023	1			T1	410		T2	9393		T3	105
valid_sources[0x6c]	1361520	1			T1	437		T2	9437		T3	125
valid_sources[0x6d]	1357985	1			T1	422		T2	9399		T3	85
valid_sources[0x6e]	1360287	1			T1	462		T2	9310		T3	225
valid_sources[0x6f]	1367898	1			T1	449		T2	9368		T3	158
valid_sources[0x70]	1364702	1			T1	391		T2	9549		T3	218
valid_sources[0x71]	1366921	1			T1	511		T2	9364		T3	270
valid_sources[0x72]	1516064	1			T1	368		T2	9545		T3	168
valid_sources[0x73]	1431510	1			T1	415		T2	9379		T3	62
valid_sources[0x74]	2075051	1			T1	470		T2	9422		T3	89
valid_sources[0x75]	3408278	1			T1	449		T2	9512		T3	130
valid_sources[0x76]	1362812	1			T1	386		T2	9340		T3	147
valid_sources[0x77]	1356837	1			T1	468		T2	9589		T3	137
valid_sources[0x78]	2278792	1			T1	476		T2	9516		T3	11
valid_sources[0x79]	1363526	1			T1	393		T2	9595		T3	242
valid_sources[0x7a]	3418967	1			T1	403		T2	9273		T3	287
valid_sources[0x7b]	1362127	1			T1	376		T2	9359		T3	98
valid_sources[0x7c]	1357631	1			T1	398		T2	9424		T3	118
valid_sources[0x7d]	2997016	1			T1	425		T2	9382		T3	66
valid_sources[0x7e]	1360724	1			T1	417		T2	9369		T3	292
valid_sources[0x7f]	3392969	1			T1	417		T2	9492		T3	100
valid_sources[0x80]	1513159	1			T1	427		T2	9318		T3	261

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

87073361

1

T1

47543

T2

425228

T3

17445

values[0x0]

all_enables

biggest_size

60365735

1

T1

10256

T2

312499

T3

3241

values[0x1]

all_enables

biggest_size

51817193

1

T1

8732

T2

264989

T3

2739