Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

253644122

1

T1

42076

T2

140444

T3

12787

full_word

199257205

1

T1

66531

T2

100271

T3

23425

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	452901017	1			T1	108607		T2	240716		T3	36212
auto[TlIntgErrCmd]	103	1			T51	4		T97	4		T98	6
auto[TlIntgErrData]	106	1			T51	2		T97	10		T98	5
auto[TlIntgErrBoth]	101	1			T51	4		T97	6		T98	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

239321735

1

T1

74312

T2

126552

T3

25699

auto[1]

213579592

1

T1

34295

T2

114163

T3

10513

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	152248031	1			T1	26769		T2	840300		T3	8254
auto[TlIntgErrNone]	partial	auto[1]	101395807	1			T1	15307		T2	564146		T3	4533
auto[TlIntgErrNone]	full_word	auto[0]	87073572	1			T1	47543		T2	425228		T3	17445
auto[TlIntgErrNone]	full_word	auto[1]	112183607	1			T1	18988		T2	577488		T3	5980
auto[TlIntgErrCmd]	partial	auto[0]	45	1			T51	3		T97	1		T98	4
auto[TlIntgErrCmd]	partial	auto[1]	50	1			T51	1		T97	3		T98	1
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T161	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T98	1		T158	1		T160	1
auto[TlIntgErrData]	partial	auto[0]	44	1			T51	1		T97	4		T98	1
auto[TlIntgErrData]	partial	auto[1]	55	1			T51	1		T97	6		T98	4
auto[TlIntgErrData]	full_word	auto[0]	3	1			T161	1		T162	1		T163	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T158	1		T157	1		T164	2
auto[TlIntgErrBoth]	partial	auto[0]	33	1			T51	1		T97	4		T98	3
auto[TlIntgErrBoth]	partial	auto[1]	57	1			T51	2		T97	2		T98	6
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T51	1		T159	1		T165	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T156	1		T166	1		T164	1