Line Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_reqfifo
| Total | Covered | Percent |
Conditions | 16 | 11 | 68.75 |
Logical | 16 | 11 | 68.75 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T12,T13,T14 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
225275664 |
0 |
0 |
T1 |
318370 |
14520 |
0 |
0 |
T2 |
505507 |
556047 |
0 |
0 |
T3 |
192821 |
4255 |
0 |
0 |
T12 |
256448 |
251646 |
0 |
0 |
T13 |
709380 |
241482 |
0 |
0 |
T14 |
957718 |
18526 |
0 |
0 |
T15 |
993238 |
113697 |
0 |
0 |
T16 |
158489 |
161298 |
0 |
0 |
T17 |
367021 |
4648 |
0 |
0 |
T18 |
6856 |
273 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
318370 |
318282 |
0 |
0 |
T2 |
505507 |
505500 |
0 |
0 |
T3 |
192821 |
192734 |
0 |
0 |
T12 |
256448 |
256447 |
0 |
0 |
T13 |
709380 |
709373 |
0 |
0 |
T14 |
957718 |
957650 |
0 |
0 |
T15 |
993238 |
993166 |
0 |
0 |
T16 |
158489 |
158480 |
0 |
0 |
T17 |
367021 |
366951 |
0 |
0 |
T18 |
6856 |
6773 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
318370 |
318282 |
0 |
0 |
T2 |
505507 |
505500 |
0 |
0 |
T3 |
192821 |
192734 |
0 |
0 |
T12 |
256448 |
256447 |
0 |
0 |
T13 |
709380 |
709373 |
0 |
0 |
T14 |
957718 |
957650 |
0 |
0 |
T15 |
993238 |
993166 |
0 |
0 |
T16 |
158489 |
158480 |
0 |
0 |
T17 |
367021 |
366951 |
0 |
0 |
T18 |
6856 |
6773 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
318370 |
318282 |
0 |
0 |
T2 |
505507 |
505500 |
0 |
0 |
T3 |
192821 |
192734 |
0 |
0 |
T12 |
256448 |
256447 |
0 |
0 |
T13 |
709380 |
709373 |
0 |
0 |
T14 |
957718 |
957650 |
0 |
0 |
T15 |
993238 |
993166 |
0 |
0 |
T16 |
158489 |
158480 |
0 |
0 |
T17 |
367021 |
366951 |
0 |
0 |
T18 |
6856 |
6773 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
225275664 |
0 |
0 |
T1 |
318370 |
14520 |
0 |
0 |
T2 |
505507 |
556047 |
0 |
0 |
T3 |
192821 |
4255 |
0 |
0 |
T12 |
256448 |
251646 |
0 |
0 |
T13 |
709380 |
241482 |
0 |
0 |
T14 |
957718 |
18526 |
0 |
0 |
T15 |
993238 |
113697 |
0 |
0 |
T16 |
158489 |
161298 |
0 |
0 |
T17 |
367021 |
4648 |
0 |
0 |
T18 |
6856 |
273 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 11 | 78.57 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 0 | 0 | |
CONT_ASSIGN | 108 | 1 | 0 | 0.00 |
ALWAYS | 111 | 2 | 1 | 50.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 0 | 0.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
|
unreachable |
108 |
0 |
1 |
111 |
1 |
1 |
112 |
0 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
0 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo
| Total | Covered | Percent |
Conditions | 13 | 5 | 38.46 |
Logical | 13 | 5 | 38.46 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Not Covered | |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Unreachable | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
5 |
71.43 |
TERNARY |
138 |
2 |
1 |
50.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
2 |
1 |
50.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Not Covered |
|
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
0 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
318370 |
318282 |
0 |
0 |
T2 |
505507 |
505500 |
0 |
0 |
T3 |
192821 |
192734 |
0 |
0 |
T12 |
256448 |
256447 |
0 |
0 |
T13 |
709380 |
709373 |
0 |
0 |
T14 |
957718 |
957650 |
0 |
0 |
T15 |
993238 |
993166 |
0 |
0 |
T16 |
158489 |
158480 |
0 |
0 |
T17 |
367021 |
366951 |
0 |
0 |
T18 |
6856 |
6773 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
318370 |
318282 |
0 |
0 |
T2 |
505507 |
505500 |
0 |
0 |
T3 |
192821 |
192734 |
0 |
0 |
T12 |
256448 |
256447 |
0 |
0 |
T13 |
709380 |
709373 |
0 |
0 |
T14 |
957718 |
957650 |
0 |
0 |
T15 |
993238 |
993166 |
0 |
0 |
T16 |
158489 |
158480 |
0 |
0 |
T17 |
367021 |
366951 |
0 |
0 |
T18 |
6856 |
6773 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
318370 |
318282 |
0 |
0 |
T2 |
505507 |
505500 |
0 |
0 |
T3 |
192821 |
192734 |
0 |
0 |
T12 |
256448 |
256447 |
0 |
0 |
T13 |
709380 |
709373 |
0 |
0 |
T14 |
957718 |
957650 |
0 |
0 |
T15 |
993238 |
993166 |
0 |
0 |
T16 |
158489 |
158480 |
0 |
0 |
T17 |
367021 |
366951 |
0 |
0 |
T18 |
6856 |
6773 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 13 | 12 | 92.31 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 0 | 0 | |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 0 | 0.00 |
ALWAYS | 111 | 1 | 1 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
|
unreachable |
101 |
1 |
1 |
108 |
0 |
1 |
111 |
1 |
1 |
112 |
|
unreachable |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_rspfifo
| Total | Covered | Percent |
Conditions | 17 | 8 | 47.06 |
Logical | 17 | 8 | 47.06 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Unreachable | |
1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | Unreachable | |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Not Covered | |
LINE 130
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Unreachable | |
LINE 130
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Unreachable | |
LINE 131
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Unreachable | |
1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
6 |
85.71 |
TERNARY |
130 |
1 |
1 |
100.00 |
TERNARY |
138 |
2 |
1 |
50.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?
Branches:
-1- | Status | Tests |
1 |
Unreachable |
|
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Unreachable |
|
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
0 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
318370 |
318282 |
0 |
0 |
T2 |
505507 |
505500 |
0 |
0 |
T3 |
192821 |
192734 |
0 |
0 |
T12 |
256448 |
256447 |
0 |
0 |
T13 |
709380 |
709373 |
0 |
0 |
T14 |
957718 |
957650 |
0 |
0 |
T15 |
993238 |
993166 |
0 |
0 |
T16 |
158489 |
158480 |
0 |
0 |
T17 |
367021 |
366951 |
0 |
0 |
T18 |
6856 |
6773 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
318370 |
318282 |
0 |
0 |
T2 |
505507 |
505500 |
0 |
0 |
T3 |
192821 |
192734 |
0 |
0 |
T12 |
256448 |
256447 |
0 |
0 |
T13 |
709380 |
709373 |
0 |
0 |
T14 |
957718 |
957650 |
0 |
0 |
T15 |
993238 |
993166 |
0 |
0 |
T16 |
158489 |
158480 |
0 |
0 |
T17 |
367021 |
366951 |
0 |
0 |
T18 |
6856 |
6773 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
318370 |
318282 |
0 |
0 |
T2 |
505507 |
505500 |
0 |
0 |
T3 |
192821 |
192734 |
0 |
0 |
T12 |
256448 |
256447 |
0 |
0 |
T13 |
709380 |
709373 |
0 |
0 |
T14 |
957718 |
957650 |
0 |
0 |
T15 |
993238 |
993166 |
0 |
0 |
T16 |
158489 |
158480 |
0 |
0 |
T17 |
367021 |
366951 |
0 |
0 |
T18 |
6856 |
6773 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_msgfifo.u_msgfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 14 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 2 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
120 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
130 |
1 |
1 |
131 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_msgfifo.u_msgfifo
| Total | Covered | Percent |
Conditions | 24 | 21 | 87.50 |
Logical | 24 | 21 | 87.50 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T37,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T14,T5,T24 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 130
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 130
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 131
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (72'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_msgfifo.u_msgfifo
| Line No. | Total | Covered | Percent |
Branches |
|
9 |
9 |
100.00 |
TERNARY |
130 |
2 |
2 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_msgfifo.u_msgfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
60488468 |
0 |
0 |
T1 |
318370 |
16190 |
0 |
0 |
T2 |
505507 |
338485 |
0 |
0 |
T3 |
192821 |
5077 |
0 |
0 |
T12 |
256448 |
241576 |
0 |
0 |
T13 |
709380 |
105528 |
0 |
0 |
T14 |
957718 |
9821 |
0 |
0 |
T15 |
993238 |
73092 |
0 |
0 |
T16 |
158489 |
141391 |
0 |
0 |
T17 |
367021 |
470 |
0 |
0 |
T18 |
6856 |
677 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
318370 |
318282 |
0 |
0 |
T2 |
505507 |
505500 |
0 |
0 |
T3 |
192821 |
192734 |
0 |
0 |
T12 |
256448 |
256447 |
0 |
0 |
T13 |
709380 |
709373 |
0 |
0 |
T14 |
957718 |
957650 |
0 |
0 |
T15 |
993238 |
993166 |
0 |
0 |
T16 |
158489 |
158480 |
0 |
0 |
T17 |
367021 |
366951 |
0 |
0 |
T18 |
6856 |
6773 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
318370 |
318282 |
0 |
0 |
T2 |
505507 |
505500 |
0 |
0 |
T3 |
192821 |
192734 |
0 |
0 |
T12 |
256448 |
256447 |
0 |
0 |
T13 |
709380 |
709373 |
0 |
0 |
T14 |
957718 |
957650 |
0 |
0 |
T15 |
993238 |
993166 |
0 |
0 |
T16 |
158489 |
158480 |
0 |
0 |
T17 |
367021 |
366951 |
0 |
0 |
T18 |
6856 |
6773 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
318370 |
318282 |
0 |
0 |
T2 |
505507 |
505500 |
0 |
0 |
T3 |
192821 |
192734 |
0 |
0 |
T12 |
256448 |
256447 |
0 |
0 |
T13 |
709380 |
709373 |
0 |
0 |
T14 |
957718 |
957650 |
0 |
0 |
T15 |
993238 |
993166 |
0 |
0 |
T16 |
158489 |
158480 |
0 |
0 |
T17 |
367021 |
366951 |
0 |
0 |
T18 |
6856 |
6773 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
60488468 |
0 |
0 |
T1 |
318370 |
16190 |
0 |
0 |
T2 |
505507 |
338485 |
0 |
0 |
T3 |
192821 |
5077 |
0 |
0 |
T12 |
256448 |
241576 |
0 |
0 |
T13 |
709380 |
105528 |
0 |
0 |
T14 |
957718 |
9821 |
0 |
0 |
T15 |
993238 |
73092 |
0 |
0 |
T16 |
158489 |
141391 |
0 |
0 |
T17 |
367021 |
470 |
0 |
0 |
T18 |
6856 |
677 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_reqfifo
| Total | Covered | Percent |
Conditions | 16 | 11 | 68.75 |
Logical | 16 | 11 | 68.75 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T12,T13,T14 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
75120436 |
0 |
0 |
T1 |
318370 |
39778 |
0 |
0 |
T2 |
505507 |
144085 |
0 |
0 |
T3 |
192821 |
15178 |
0 |
0 |
T12 |
256448 |
647418 |
0 |
0 |
T13 |
709380 |
59630 |
0 |
0 |
T14 |
957718 |
51301 |
0 |
0 |
T15 |
993238 |
28601 |
0 |
0 |
T16 |
158489 |
50739 |
0 |
0 |
T17 |
367021 |
82577 |
0 |
0 |
T18 |
6856 |
546 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
318370 |
318282 |
0 |
0 |
T2 |
505507 |
505500 |
0 |
0 |
T3 |
192821 |
192734 |
0 |
0 |
T12 |
256448 |
256447 |
0 |
0 |
T13 |
709380 |
709373 |
0 |
0 |
T14 |
957718 |
957650 |
0 |
0 |
T15 |
993238 |
993166 |
0 |
0 |
T16 |
158489 |
158480 |
0 |
0 |
T17 |
367021 |
366951 |
0 |
0 |
T18 |
6856 |
6773 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
318370 |
318282 |
0 |
0 |
T2 |
505507 |
505500 |
0 |
0 |
T3 |
192821 |
192734 |
0 |
0 |
T12 |
256448 |
256447 |
0 |
0 |
T13 |
709380 |
709373 |
0 |
0 |
T14 |
957718 |
957650 |
0 |
0 |
T15 |
993238 |
993166 |
0 |
0 |
T16 |
158489 |
158480 |
0 |
0 |
T17 |
367021 |
366951 |
0 |
0 |
T18 |
6856 |
6773 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
318370 |
318282 |
0 |
0 |
T2 |
505507 |
505500 |
0 |
0 |
T3 |
192821 |
192734 |
0 |
0 |
T12 |
256448 |
256447 |
0 |
0 |
T13 |
709380 |
709373 |
0 |
0 |
T14 |
957718 |
957650 |
0 |
0 |
T15 |
993238 |
993166 |
0 |
0 |
T16 |
158489 |
158480 |
0 |
0 |
T17 |
367021 |
366951 |
0 |
0 |
T18 |
6856 |
6773 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
75120436 |
0 |
0 |
T1 |
318370 |
39778 |
0 |
0 |
T2 |
505507 |
144085 |
0 |
0 |
T3 |
192821 |
15178 |
0 |
0 |
T12 |
256448 |
647418 |
0 |
0 |
T13 |
709380 |
59630 |
0 |
0 |
T14 |
957718 |
51301 |
0 |
0 |
T15 |
993238 |
28601 |
0 |
0 |
T16 |
158489 |
50739 |
0 |
0 |
T17 |
367021 |
82577 |
0 |
0 |
T18 |
6856 |
546 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo
| Total | Covered | Percent |
Conditions | 16 | 10 | 62.50 |
Logical | 16 | 10 | 62.50 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
36672824 |
0 |
0 |
T1 |
318370 |
39778 |
0 |
0 |
T2 |
505507 |
144085 |
0 |
0 |
T3 |
192821 |
15178 |
0 |
0 |
T12 |
256448 |
144085 |
0 |
0 |
T13 |
709380 |
59630 |
0 |
0 |
T14 |
957718 |
51301 |
0 |
0 |
T15 |
993238 |
28601 |
0 |
0 |
T16 |
158489 |
50739 |
0 |
0 |
T17 |
367021 |
18498 |
0 |
0 |
T18 |
6856 |
546 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
318370 |
318282 |
0 |
0 |
T2 |
505507 |
505500 |
0 |
0 |
T3 |
192821 |
192734 |
0 |
0 |
T12 |
256448 |
256447 |
0 |
0 |
T13 |
709380 |
709373 |
0 |
0 |
T14 |
957718 |
957650 |
0 |
0 |
T15 |
993238 |
993166 |
0 |
0 |
T16 |
158489 |
158480 |
0 |
0 |
T17 |
367021 |
366951 |
0 |
0 |
T18 |
6856 |
6773 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
318370 |
318282 |
0 |
0 |
T2 |
505507 |
505500 |
0 |
0 |
T3 |
192821 |
192734 |
0 |
0 |
T12 |
256448 |
256447 |
0 |
0 |
T13 |
709380 |
709373 |
0 |
0 |
T14 |
957718 |
957650 |
0 |
0 |
T15 |
993238 |
993166 |
0 |
0 |
T16 |
158489 |
158480 |
0 |
0 |
T17 |
367021 |
366951 |
0 |
0 |
T18 |
6856 |
6773 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
318370 |
318282 |
0 |
0 |
T2 |
505507 |
505500 |
0 |
0 |
T3 |
192821 |
192734 |
0 |
0 |
T12 |
256448 |
256447 |
0 |
0 |
T13 |
709380 |
709373 |
0 |
0 |
T14 |
957718 |
957650 |
0 |
0 |
T15 |
993238 |
993166 |
0 |
0 |
T16 |
158489 |
158480 |
0 |
0 |
T17 |
367021 |
366951 |
0 |
0 |
T18 |
6856 |
6773 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
36672824 |
0 |
0 |
T1 |
318370 |
39778 |
0 |
0 |
T2 |
505507 |
144085 |
0 |
0 |
T3 |
192821 |
15178 |
0 |
0 |
T12 |
256448 |
144085 |
0 |
0 |
T13 |
709380 |
59630 |
0 |
0 |
T14 |
957718 |
51301 |
0 |
0 |
T15 |
993238 |
28601 |
0 |
0 |
T16 |
158489 |
50739 |
0 |
0 |
T17 |
367021 |
18498 |
0 |
0 |
T18 |
6856 |
546 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_rspfifo
| Total | Covered | Percent |
Conditions | 24 | 18 | 75.00 |
Logical | 24 | 18 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T12,T17,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T12,T13,T14 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 130
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 130
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 131
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T12,T17,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
9 |
9 |
100.00 |
TERNARY |
130 |
2 |
2 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
75120436 |
0 |
0 |
T1 |
318370 |
39778 |
0 |
0 |
T2 |
505507 |
144085 |
0 |
0 |
T3 |
192821 |
15178 |
0 |
0 |
T12 |
256448 |
647418 |
0 |
0 |
T13 |
709380 |
59630 |
0 |
0 |
T14 |
957718 |
51301 |
0 |
0 |
T15 |
993238 |
28601 |
0 |
0 |
T16 |
158489 |
50739 |
0 |
0 |
T17 |
367021 |
82577 |
0 |
0 |
T18 |
6856 |
546 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
318370 |
318282 |
0 |
0 |
T2 |
505507 |
505500 |
0 |
0 |
T3 |
192821 |
192734 |
0 |
0 |
T12 |
256448 |
256447 |
0 |
0 |
T13 |
709380 |
709373 |
0 |
0 |
T14 |
957718 |
957650 |
0 |
0 |
T15 |
993238 |
993166 |
0 |
0 |
T16 |
158489 |
158480 |
0 |
0 |
T17 |
367021 |
366951 |
0 |
0 |
T18 |
6856 |
6773 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
318370 |
318282 |
0 |
0 |
T2 |
505507 |
505500 |
0 |
0 |
T3 |
192821 |
192734 |
0 |
0 |
T12 |
256448 |
256447 |
0 |
0 |
T13 |
709380 |
709373 |
0 |
0 |
T14 |
957718 |
957650 |
0 |
0 |
T15 |
993238 |
993166 |
0 |
0 |
T16 |
158489 |
158480 |
0 |
0 |
T17 |
367021 |
366951 |
0 |
0 |
T18 |
6856 |
6773 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
318370 |
318282 |
0 |
0 |
T2 |
505507 |
505500 |
0 |
0 |
T3 |
192821 |
192734 |
0 |
0 |
T12 |
256448 |
256447 |
0 |
0 |
T13 |
709380 |
709373 |
0 |
0 |
T14 |
957718 |
957650 |
0 |
0 |
T15 |
993238 |
993166 |
0 |
0 |
T16 |
158489 |
158480 |
0 |
0 |
T17 |
367021 |
366951 |
0 |
0 |
T18 |
6856 |
6773 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
75120436 |
0 |
0 |
T1 |
318370 |
39778 |
0 |
0 |
T2 |
505507 |
144085 |
0 |
0 |
T3 |
192821 |
15178 |
0 |
0 |
T12 |
256448 |
647418 |
0 |
0 |
T13 |
709380 |
59630 |
0 |
0 |
T14 |
957718 |
51301 |
0 |
0 |
T15 |
993238 |
28601 |
0 |
0 |
T16 |
158489 |
50739 |
0 |
0 |
T17 |
367021 |
82577 |
0 |
0 |
T18 |
6856 |
546 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
466804900 |
0 |
0 |
T1 |
318370 |
125179 |
0 |
0 |
T2 |
505507 |
240716 |
0 |
0 |
T3 |
192821 |
39202 |
0 |
0 |
T12 |
256448 |
242015 |
0 |
0 |
T13 |
709380 |
105696 |
0 |
0 |
T14 |
957718 |
137824 |
0 |
0 |
T15 |
993238 |
612464 |
0 |
0 |
T16 |
158489 |
242755 |
0 |
0 |
T17 |
367021 |
34303 |
0 |
0 |
T18 |
6856 |
2204 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
318370 |
318282 |
0 |
0 |
T2 |
505507 |
505500 |
0 |
0 |
T3 |
192821 |
192734 |
0 |
0 |
T12 |
256448 |
256447 |
0 |
0 |
T13 |
709380 |
709373 |
0 |
0 |
T14 |
957718 |
957650 |
0 |
0 |
T15 |
993238 |
993166 |
0 |
0 |
T16 |
158489 |
158480 |
0 |
0 |
T17 |
367021 |
366951 |
0 |
0 |
T18 |
6856 |
6773 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
318370 |
318282 |
0 |
0 |
T2 |
505507 |
505500 |
0 |
0 |
T3 |
192821 |
192734 |
0 |
0 |
T12 |
256448 |
256447 |
0 |
0 |
T13 |
709380 |
709373 |
0 |
0 |
T14 |
957718 |
957650 |
0 |
0 |
T15 |
993238 |
993166 |
0 |
0 |
T16 |
158489 |
158480 |
0 |
0 |
T17 |
367021 |
366951 |
0 |
0 |
T18 |
6856 |
6773 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
318370 |
318282 |
0 |
0 |
T2 |
505507 |
505500 |
0 |
0 |
T3 |
192821 |
192734 |
0 |
0 |
T12 |
256448 |
256447 |
0 |
0 |
T13 |
709380 |
709373 |
0 |
0 |
T14 |
957718 |
957650 |
0 |
0 |
T15 |
993238 |
993166 |
0 |
0 |
T16 |
158489 |
158480 |
0 |
0 |
T17 |
367021 |
366951 |
0 |
0 |
T18 |
6856 |
6773 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1238 |
1238 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
948641900 |
0 |
0 |
T1 |
318370 |
108607 |
0 |
0 |
T2 |
505507 |
240716 |
0 |
0 |
T3 |
192821 |
36212 |
0 |
0 |
T12 |
256448 |
108939 |
0 |
0 |
T13 |
709380 |
103765 |
0 |
0 |
T14 |
957718 |
135887 |
0 |
0 |
T15 |
993238 |
491642 |
0 |
0 |
T16 |
158489 |
234981 |
0 |
0 |
T17 |
367021 |
148665 |
0 |
0 |
T18 |
6856 |
2204 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
318370 |
318282 |
0 |
0 |
T2 |
505507 |
505500 |
0 |
0 |
T3 |
192821 |
192734 |
0 |
0 |
T12 |
256448 |
256447 |
0 |
0 |
T13 |
709380 |
709373 |
0 |
0 |
T14 |
957718 |
957650 |
0 |
0 |
T15 |
993238 |
993166 |
0 |
0 |
T16 |
158489 |
158480 |
0 |
0 |
T17 |
367021 |
366951 |
0 |
0 |
T18 |
6856 |
6773 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
318370 |
318282 |
0 |
0 |
T2 |
505507 |
505500 |
0 |
0 |
T3 |
192821 |
192734 |
0 |
0 |
T12 |
256448 |
256447 |
0 |
0 |
T13 |
709380 |
709373 |
0 |
0 |
T14 |
957718 |
957650 |
0 |
0 |
T15 |
993238 |
993166 |
0 |
0 |
T16 |
158489 |
158480 |
0 |
0 |
T17 |
367021 |
366951 |
0 |
0 |
T18 |
6856 |
6773 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
318370 |
318282 |
0 |
0 |
T2 |
505507 |
505500 |
0 |
0 |
T3 |
192821 |
192734 |
0 |
0 |
T12 |
256448 |
256447 |
0 |
0 |
T13 |
709380 |
709373 |
0 |
0 |
T14 |
957718 |
957650 |
0 |
0 |
T15 |
993238 |
993166 |
0 |
0 |
T16 |
158489 |
158480 |
0 |
0 |
T17 |
367021 |
366951 |
0 |
0 |
T18 |
6856 |
6773 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1238 |
1238 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
36680770 |
0 |
0 |
T1 |
318370 |
39778 |
0 |
0 |
T2 |
505507 |
144085 |
0 |
0 |
T3 |
192821 |
15178 |
0 |
0 |
T12 |
256448 |
144085 |
0 |
0 |
T13 |
709380 |
59630 |
0 |
0 |
T14 |
957718 |
51301 |
0 |
0 |
T15 |
993238 |
28601 |
0 |
0 |
T16 |
158489 |
50739 |
0 |
0 |
T17 |
367021 |
18498 |
0 |
0 |
T18 |
6856 |
546 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
318370 |
318282 |
0 |
0 |
T2 |
505507 |
505500 |
0 |
0 |
T3 |
192821 |
192734 |
0 |
0 |
T12 |
256448 |
256447 |
0 |
0 |
T13 |
709380 |
709373 |
0 |
0 |
T14 |
957718 |
957650 |
0 |
0 |
T15 |
993238 |
993166 |
0 |
0 |
T16 |
158489 |
158480 |
0 |
0 |
T17 |
367021 |
366951 |
0 |
0 |
T18 |
6856 |
6773 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
318370 |
318282 |
0 |
0 |
T2 |
505507 |
505500 |
0 |
0 |
T3 |
192821 |
192734 |
0 |
0 |
T12 |
256448 |
256447 |
0 |
0 |
T13 |
709380 |
709373 |
0 |
0 |
T14 |
957718 |
957650 |
0 |
0 |
T15 |
993238 |
993166 |
0 |
0 |
T16 |
158489 |
158480 |
0 |
0 |
T17 |
367021 |
366951 |
0 |
0 |
T18 |
6856 |
6773 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
318370 |
318282 |
0 |
0 |
T2 |
505507 |
505500 |
0 |
0 |
T3 |
192821 |
192734 |
0 |
0 |
T12 |
256448 |
256447 |
0 |
0 |
T13 |
709380 |
709373 |
0 |
0 |
T14 |
957718 |
957650 |
0 |
0 |
T15 |
993238 |
993166 |
0 |
0 |
T16 |
158489 |
158480 |
0 |
0 |
T17 |
367021 |
366951 |
0 |
0 |
T18 |
6856 |
6773 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1238 |
1238 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
75127759 |
0 |
0 |
T1 |
318370 |
39778 |
0 |
0 |
T2 |
505507 |
144085 |
0 |
0 |
T3 |
192821 |
15178 |
0 |
0 |
T12 |
256448 |
647418 |
0 |
0 |
T13 |
709380 |
59630 |
0 |
0 |
T14 |
957718 |
51301 |
0 |
0 |
T15 |
993238 |
28601 |
0 |
0 |
T16 |
158489 |
50739 |
0 |
0 |
T17 |
367021 |
82577 |
0 |
0 |
T18 |
6856 |
546 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
318370 |
318282 |
0 |
0 |
T2 |
505507 |
505500 |
0 |
0 |
T3 |
192821 |
192734 |
0 |
0 |
T12 |
256448 |
256447 |
0 |
0 |
T13 |
709380 |
709373 |
0 |
0 |
T14 |
957718 |
957650 |
0 |
0 |
T15 |
993238 |
993166 |
0 |
0 |
T16 |
158489 |
158480 |
0 |
0 |
T17 |
367021 |
366951 |
0 |
0 |
T18 |
6856 |
6773 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
318370 |
318282 |
0 |
0 |
T2 |
505507 |
505500 |
0 |
0 |
T3 |
192821 |
192734 |
0 |
0 |
T12 |
256448 |
256447 |
0 |
0 |
T13 |
709380 |
709373 |
0 |
0 |
T14 |
957718 |
957650 |
0 |
0 |
T15 |
993238 |
993166 |
0 |
0 |
T16 |
158489 |
158480 |
0 |
0 |
T17 |
367021 |
366951 |
0 |
0 |
T18 |
6856 |
6773 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
318370 |
318282 |
0 |
0 |
T2 |
505507 |
505500 |
0 |
0 |
T3 |
192821 |
192734 |
0 |
0 |
T12 |
256448 |
256447 |
0 |
0 |
T13 |
709380 |
709373 |
0 |
0 |
T14 |
957718 |
957650 |
0 |
0 |
T15 |
993238 |
993166 |
0 |
0 |
T16 |
158489 |
158480 |
0 |
0 |
T17 |
367021 |
366951 |
0 |
0 |
T18 |
6856 |
6773 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1238 |
1238 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
110911728 |
0 |
0 |
T1 |
318370 |
14520 |
0 |
0 |
T2 |
505507 |
556047 |
0 |
0 |
T3 |
192821 |
4255 |
0 |
0 |
T12 |
256448 |
559292 |
0 |
0 |
T13 |
709380 |
241482 |
0 |
0 |
T14 |
957718 |
18526 |
0 |
0 |
T15 |
993238 |
113697 |
0 |
0 |
T16 |
158489 |
168400 |
0 |
0 |
T17 |
367021 |
994 |
0 |
0 |
T18 |
6856 |
273 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
318370 |
318282 |
0 |
0 |
T2 |
505507 |
505500 |
0 |
0 |
T3 |
192821 |
192734 |
0 |
0 |
T12 |
256448 |
256447 |
0 |
0 |
T13 |
709380 |
709373 |
0 |
0 |
T14 |
957718 |
957650 |
0 |
0 |
T15 |
993238 |
993166 |
0 |
0 |
T16 |
158489 |
158480 |
0 |
0 |
T17 |
367021 |
366951 |
0 |
0 |
T18 |
6856 |
6773 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
318370 |
318282 |
0 |
0 |
T2 |
505507 |
505500 |
0 |
0 |
T3 |
192821 |
192734 |
0 |
0 |
T12 |
256448 |
256447 |
0 |
0 |
T13 |
709380 |
709373 |
0 |
0 |
T14 |
957718 |
957650 |
0 |
0 |
T15 |
993238 |
993166 |
0 |
0 |
T16 |
158489 |
158480 |
0 |
0 |
T17 |
367021 |
366951 |
0 |
0 |
T18 |
6856 |
6773 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
318370 |
318282 |
0 |
0 |
T2 |
505507 |
505500 |
0 |
0 |
T3 |
192821 |
192734 |
0 |
0 |
T12 |
256448 |
256447 |
0 |
0 |
T13 |
709380 |
709373 |
0 |
0 |
T14 |
957718 |
957650 |
0 |
0 |
T15 |
993238 |
993166 |
0 |
0 |
T16 |
158489 |
158480 |
0 |
0 |
T17 |
367021 |
366951 |
0 |
0 |
T18 |
6856 |
6773 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1238 |
1238 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
225306309 |
0 |
0 |
T1 |
318370 |
14520 |
0 |
0 |
T2 |
505507 |
556047 |
0 |
0 |
T3 |
192821 |
4255 |
0 |
0 |
T12 |
256448 |
251646 |
0 |
0 |
T13 |
709380 |
241482 |
0 |
0 |
T14 |
957718 |
18526 |
0 |
0 |
T15 |
993238 |
113697 |
0 |
0 |
T16 |
158489 |
161298 |
0 |
0 |
T17 |
367021 |
4648 |
0 |
0 |
T18 |
6856 |
273 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
318370 |
318282 |
0 |
0 |
T2 |
505507 |
505500 |
0 |
0 |
T3 |
192821 |
192734 |
0 |
0 |
T12 |
256448 |
256447 |
0 |
0 |
T13 |
709380 |
709373 |
0 |
0 |
T14 |
957718 |
957650 |
0 |
0 |
T15 |
993238 |
993166 |
0 |
0 |
T16 |
158489 |
158480 |
0 |
0 |
T17 |
367021 |
366951 |
0 |
0 |
T18 |
6856 |
6773 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
318370 |
318282 |
0 |
0 |
T2 |
505507 |
505500 |
0 |
0 |
T3 |
192821 |
192734 |
0 |
0 |
T12 |
256448 |
256447 |
0 |
0 |
T13 |
709380 |
709373 |
0 |
0 |
T14 |
957718 |
957650 |
0 |
0 |
T15 |
993238 |
993166 |
0 |
0 |
T16 |
158489 |
158480 |
0 |
0 |
T17 |
367021 |
366951 |
0 |
0 |
T18 |
6856 |
6773 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
318370 |
318282 |
0 |
0 |
T2 |
505507 |
505500 |
0 |
0 |
T3 |
192821 |
192734 |
0 |
0 |
T12 |
256448 |
256447 |
0 |
0 |
T13 |
709380 |
709373 |
0 |
0 |
T14 |
957718 |
957650 |
0 |
0 |
T15 |
993238 |
993166 |
0 |
0 |
T16 |
158489 |
158480 |
0 |
0 |
T17 |
367021 |
366951 |
0 |
0 |
T18 |
6856 |
6773 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1238 |
1238 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |