Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	3296	0	0
entropy_period_rd_A	2147483647	2014	0	0
intr_enable_rd_A	2147483647	2657	0	0
prefix_0_rd_A	2147483647	1734	0	0
prefix_10_rd_A	2147483647	1797	0	0
prefix_1_rd_A	2147483647	1769	0	0
prefix_2_rd_A	2147483647	1691	0	0
prefix_3_rd_A	2147483647	1739	0	0
prefix_4_rd_A	2147483647	1778	0	0
prefix_5_rd_A	2147483647	1771	0	0
prefix_6_rd_A	2147483647	1761	0	0
prefix_7_rd_A	2147483647	1756	0	0
prefix_8_rd_A	2147483647	1717	0	0
prefix_9_rd_A	2147483647	1732	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3296	0	0
T51	4765	1	0	0
T52	8160	132	0	0
T53	2943	182	0	0
T95	3834	25	0	0
T96	7913	156	0	0
T97	30211	2	0	0
T98	8607	1	0	0
T99	2841	164	0	0
T110	4643	47	0	0
T115	8092	3	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2014	0	0
T89	12078	95	0	0
T90	13411	81	0	0
T97	30211	153	0	0
T115	8092	19	0	0
T117	4180	6	0	0
T127	2823	10	0	0
T128	1600	3	0	0
T129	3290	17	0	0
T130	5300	8	0	0
T131	124948	107	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2657	0	0
T89	12078	96	0	0
T90	13411	83	0	0
T97	30211	127	0	0
T115	8092	11	0	0
T117	4180	12	0	0
T128	1600	3	0	0
T129	3290	27	0	0
T130	5300	27	0	0
T131	124948	257	0	0
T132	1439	22	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1734	0	0
T89	12078	61	0	0
T90	13411	36	0	0
T97	30211	106	0	0
T115	8092	17	0	0
T117	4180	13	0	0
T128	1600	6	0	0
T129	3290	8	0	0
T130	5300	5	0	0
T131	124948	280	0	0
T133	1546	7	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1797	0	0
T89	12078	43	0	0
T90	13411	65	0	0
T97	30211	70	0	0
T115	8092	20	0	0
T117	4180	12	0	0
T128	1600	1	0	0
T129	3290	8	0	0
T130	5300	7	0	0
T131	124948	284	0	0
T133	1546	8	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1769	0	0
T89	12078	49	0	0
T90	13411	52	0	0
T97	30211	92	0	0
T115	8092	28	0	0
T127	2823	6	0	0
T128	1600	3	0	0
T129	3290	4	0	0
T130	5300	8	0	0
T131	124948	278	0	0
T133	1546	3	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1691	0	0
T89	12078	52	0	0
T90	13411	32	0	0
T97	30211	84	0	0
T115	8092	25	0	0
T117	4180	10	0	0
T127	2823	1	0	0
T129	3290	6	0	0
T130	5300	13	0	0
T131	124948	271	0	0
T133	1546	5	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1739	0	0
T89	12078	49	0	0
T90	13411	47	0	0
T97	30211	75	0	0
T115	8092	26	0	0
T117	4180	8	0	0
T127	2823	1	0	0
T128	1600	8	0	0
T129	3290	2	0	0
T130	5300	11	0	0
T131	124948	243	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1778	0	0
T89	12078	61	0	0
T90	13411	60	0	0
T97	30211	79	0	0
T115	8092	5	0	0
T117	4180	11	0	0
T127	2823	2	0	0
T128	1600	7	0	0
T129	3290	5	0	0
T130	5300	9	0	0
T131	124948	293	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1771	0	0
T89	12078	58	0	0
T90	13411	51	0	0
T97	30211	74	0	0
T115	8092	18	0	0
T117	4180	10	0	0
T127	2823	3	0	0
T128	1600	6	0	0
T129	3290	6	0	0
T130	5300	4	0	0
T131	124948	282	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1761	0	0
T89	12078	61	0	0
T90	13411	42	0	0
T97	30211	103	0	0
T115	8092	20	0	0
T117	4180	9	0	0
T127	2823	1	0	0
T128	1600	1	0	0
T129	3290	12	0	0
T130	5300	13	0	0
T131	124948	252	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1756	0	0
T89	12078	34	0	0
T90	13411	40	0	0
T97	30211	90	0	0
T115	8092	9	0	0
T117	4180	2	0	0
T127	2823	1	0	0
T129	3290	6	0	0
T130	5300	12	0	0
T131	124948	330	0	0
T133	1546	6	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1717	0	0
T89	12078	35	0	0
T90	13411	56	0	0
T97	30211	82	0	0
T115	8092	14	0	0
T117	4180	5	0	0
T128	1600	3	0	0
T129	3290	13	0	0
T130	5300	27	0	0
T131	124948	301	0	0
T133	1546	5	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1732	0	0
T89	12078	59	0	0
T90	13411	52	0	0
T97	30211	72	0	0
T115	8092	19	0	0
T117	4180	14	0	0
T127	2823	17	0	0
T128	1600	6	0	0
T129	3290	9	0	0
T131	124948	270	0	0
T133	1546	4	0	0