Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

253050719

1

T1

1670

T2

9582

T3

828

full_word

198632726

1

T1

2928

T2

137946

T3

1402

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	451683135	1			T1	4598		T2	147528		T3	2230
auto[TlIntgErrCmd]	96	1			T109	6		T110	3		T111	2
auto[TlIntgErrData]	101	1			T109	9		T110	2		T111	6
auto[TlIntgErrBoth]	113	1			T109	5		T110	5		T111	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

238122508

1

T1

3217

T2

42709

T3

1161

auto[1]

213560937

1

T1

1381

T2

104819

T3

1069

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrCmd]]	[full_word]	[auto[1]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	151593637	1			T1	1142		T2	7861		T3	449
auto[TlIntgErrNone]	partial	auto[1]	101456798	1			T1	528		T2	1721		T3	379
auto[TlIntgErrNone]	full_word	auto[0]	86528748	1			T1	2075		T2	34848		T3	712
auto[TlIntgErrNone]	full_word	auto[1]	112103952	1			T1	853		T2	103098		T3	690
auto[TlIntgErrCmd]	partial	auto[0]	40	1			T109	2		T110	2		T162	8
auto[TlIntgErrCmd]	partial	auto[1]	52	1			T109	4		T110	1		T111	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T111	1		T138	1		T163	1
auto[TlIntgErrData]	partial	auto[0]	39	1			T109	2		T111	3		T162	2
auto[TlIntgErrData]	partial	auto[1]	54	1			T109	6		T110	2		T111	3
auto[TlIntgErrData]	full_word	auto[0]	5	1			T109	1		T164	1		T163	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T165	1		T166	1		T167	1
auto[TlIntgErrBoth]	partial	auto[0]	33	1			T109	1		T110	3		T162	1
auto[TlIntgErrBoth]	partial	auto[1]	66	1			T109	3		T110	2		T111	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T163	1		T168	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	12	1			T109	1		T162	1		T146	1