Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	137762	0	0
entropy_period_rd_A	2147483647	1728	0	0
intr_enable_rd_A	2147483647	2706	0	0
prefix_0_rd_A	2147483647	1830	0	0
prefix_10_rd_A	2147483647	2127	0	0
prefix_1_rd_A	2147483647	2062	0	0
prefix_2_rd_A	2147483647	2098	0	0
prefix_3_rd_A	2147483647	2064	0	0
prefix_4_rd_A	2147483647	1982	0	0
prefix_5_rd_A	2147483647	2014	0	0
prefix_6_rd_A	2147483647	2068	0	0
prefix_7_rd_A	2147483647	2010	0	0
prefix_8_rd_A	2147483647	1906	0	0
prefix_9_rd_A	2147483647	1911	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	137762	0	0
T27	309714	44180	0	0
T50	0	16922	0	0
T51	0	74067	0	0
T52	181800	0	0	0
T53	353190	0	0	0
T61	85969	0	0	0
T111	0	1	0	0
T115	0	128	0	0
T116	0	1	0	0
T117	0	7	0	0
T118	0	97	0	0
T119	0	53	0	0
T120	0	5	0	0
T121	138854	0	0	0
T122	177666	0	0	0
T123	173584	0	0	0
T124	467168	0	0	0
T125	348831	0	0	0
T126	647613	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1728	0	0
T109	25610	79	0	0
T111	12795	59	0	0
T134	2713	17	0	0
T135	1792	1	0	0
T136	5819	11	0	0
T137	4197	15	0	0
T138	12039	69	0	0
T139	125193	105	0	0
T140	2273	8	0	0
T141	2457	2	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2706	0	0
T109	25610	78	0	0
T111	12795	60	0	0
T134	2713	19	0	0
T135	1792	4	0	0
T136	5819	23	0	0
T137	4197	4	0	0
T138	12039	86	0	0
T139	125193	284	0	0
T142	1436	6	0	0
T143	3089	3	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1830	0	0
T109	25610	29	0	0
T111	12795	43	0	0
T134	2713	8	0	0
T135	1792	4	0	0
T136	5819	6	0	0
T137	4197	4	0	0
T138	12039	33	0	0
T139	125193	260	0	0
T141	2457	4	0	0
T144	2781	10	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2127	0	0
T109	25610	61	0	0
T111	12795	55	0	0
T134	2713	16	0	0
T135	1792	5	0	0
T136	5819	65	0	0
T138	12039	44	0	0
T139	125193	250	0	0
T140	2273	5	0	0
T141	2457	2	0	0
T144	2781	3	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2062	0	0
T109	25610	45	0	0
T111	12795	24	0	0
T134	2713	9	0	0
T135	1792	2	0	0
T136	5819	34	0	0
T138	12039	34	0	0
T139	125193	293	0	0
T140	2273	9	0	0
T141	2457	6	0	0
T144	2781	7	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2098	0	0
T109	25610	36	0	0
T111	12795	39	0	0
T134	2713	5	0	0
T135	1792	2	0	0
T136	5819	8	0	0
T137	4197	8	0	0
T138	12039	59	0	0
T139	125193	297	0	0
T141	2457	13	0	0
T144	2781	2	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2064	0	0
T109	25610	24	0	0
T111	12795	42	0	0
T134	2713	7	0	0
T136	5819	26	0	0
T137	4197	6	0	0
T138	12039	52	0	0
T139	125193	294	0	0
T141	2457	3	0	0
T144	2781	10	0	0
T145	1835	2	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1982	0	0
T109	25610	31	0	0
T111	12795	44	0	0
T134	2713	4	0	0
T137	4197	5	0	0
T138	12039	41	0	0
T139	125193	251	0	0
T140	2273	3	0	0
T141	2457	5	0	0
T144	2781	16	0	0
T145	1835	3	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2014	0	0
T109	25610	46	0	0
T111	12795	32	0	0
T134	2713	11	0	0
T135	1792	6	0	0
T136	5819	25	0	0
T137	4197	2	0	0
T138	12039	54	0	0
T139	125193	288	0	0
T144	2781	6	0	0
T146	11488	16	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2068	0	0
T109	25610	59	0	0
T111	12795	39	0	0
T134	2713	12	0	0
T135	1792	5	0	0
T136	5819	19	0	0
T137	4197	9	0	0
T138	12039	61	0	0
T139	125193	246	0	0
T140	2273	5	0	0
T141	2457	9	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2010	0	0
T109	25610	32	0	0
T111	12795	32	0	0
T134	2713	9	0	0
T135	1792	4	0	0
T136	5819	8	0	0
T137	4197	4	0	0
T138	12039	51	0	0
T139	125193	276	0	0
T144	2781	8	0	0
T146	11488	27	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1906	0	0
T109	25610	39	0	0
T111	12795	51	0	0
T135	1792	1	0	0
T136	5819	3	0	0
T137	4197	13	0	0
T138	12039	57	0	0
T139	125193	245	0	0
T140	2273	9	0	0
T141	2457	4	0	0
T145	1835	4	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1911	0	0
T109	25610	22	0	0
T111	12795	35	0	0
T134	2713	7	0	0
T135	1792	5	0	0
T136	5819	26	0	0
T137	4197	7	0	0
T138	12039	44	0	0
T139	125193	300	0	0
T146	11488	34	0	0
T147	144803	401	0	0