Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

254397241

1

T1

401855

T2

4352

T3

399630

full_word

198822814

1

T1

261829

T2

7400

T3

261666

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	453219785	1			T1	663684		T2	11752		T3	661296
auto[TlIntgErrCmd]	90	1			T109	4		T111	2		T112	3
auto[TlIntgErrData]	86	1			T109	3		T111	4		T112	1
auto[TlIntgErrBoth]	94	1			T109	3		T111	4		T112	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

239324570

1

T1

340113

T2

8058

T3

338909

auto[1]

213895485

1

T1

323571

T2

3694

T3

322387

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	152517750	1			T1	240193		T2	2578		T3	239574
auto[TlIntgErrNone]	partial	auto[1]	101879244	1			T1	161662		T2	1774		T3	160056
auto[TlIntgErrNone]	full_word	auto[0]	86806701	1			T1	99920		T2	5480		T3	99335
auto[TlIntgErrNone]	full_word	auto[1]	112016090	1			T1	161909		T2	1920		T3	162331
auto[TlIntgErrCmd]	partial	auto[0]	36	1			T109	1		T112	2		T153	2
auto[TlIntgErrCmd]	partial	auto[1]	47	1			T109	3		T111	2		T112	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T172	1		T174	1		T175	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T173	1		T176	1		T174	1
auto[TlIntgErrData]	partial	auto[0]	40	1			T109	1		T111	1		T153	5
auto[TlIntgErrData]	partial	auto[1]	38	1			T109	1		T111	3		T112	1
auto[TlIntgErrData]	full_word	auto[0]	3	1			T176	1		T177	1		T178	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T109	1		T172	1		T174	1
auto[TlIntgErrBoth]	partial	auto[0]	31	1			T109	2		T111	2		T112	3
auto[TlIntgErrBoth]	partial	auto[1]	55	1			T111	2		T112	3		T153	4
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T179	1		T176	1		T180	2
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T109	1		T172	1		-	-