Line Coverage for Module :
kmac_core
| Line No. | Total | Covered | Percent |
TOTAL | | 69 | 68 | 98.55 |
CONT_ASSIGN | 153 | 1 | 1 | 100.00 |
ALWAYS | 161 | 3 | 3 | 100.00 |
ALWAYS | 166 | 30 | 30 | 100.00 |
CONT_ASSIGN | 251 | 1 | 1 | 100.00 |
CONT_ASSIGN | 252 | 1 | 1 | 100.00 |
CONT_ASSIGN | 253 | 1 | 1 | 100.00 |
CONT_ASSIGN | 254 | 1 | 1 | 100.00 |
CONT_ASSIGN | 258 | 1 | 1 | 100.00 |
CONT_ASSIGN | 260 | 1 | 1 | 100.00 |
CONT_ASSIGN | 265 | 1 | 1 | 100.00 |
ALWAYS | 268 | 6 | 5 | 83.33 |
CONT_ASSIGN | 287 | 1 | 1 | 100.00 |
ALWAYS | 307 | 6 | 6 | 100.00 |
ALWAYS | 338 | 6 | 6 | 100.00 |
CONT_ASSIGN | 372 | 1 | 1 | 100.00 |
CONT_ASSIGN | 394 | 1 | 1 | 100.00 |
ALWAYS | 420 | 6 | 6 | 100.00 |
CONT_ASSIGN | 431 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
153 |
1 |
1 |
161 |
3 |
3 |
166 |
1 |
1 |
168 |
1 |
1 |
169 |
1 |
1 |
171 |
1 |
1 |
173 |
1 |
1 |
174 |
1 |
1 |
176 |
1 |
1 |
178 |
1 |
1 |
180 |
1 |
1 |
181 |
1 |
1 |
183 |
1 |
1 |
190 |
1 |
1 |
191 |
1 |
1 |
193 |
1 |
1 |
194 |
1 |
1 |
196 |
1 |
1 |
197 |
1 |
1 |
199 |
1 |
1 |
201 |
1 |
1 |
207 |
1 |
1 |
208 |
1 |
1 |
210 |
1 |
1 |
212 |
1 |
1 |
217 |
1 |
1 |
218 |
1 |
1 |
220 |
1 |
1 |
226 |
1 |
1 |
227 |
1 |
1 |
240 |
1 |
1 |
241 |
1 |
1 |
|
|
|
MISSING_ELSE |
251 |
1 |
1 |
252 |
1 |
1 |
253 |
1 |
1 |
254 |
1 |
1 |
258 |
1 |
1 |
260 |
1 |
1 |
265 |
1 |
1 |
268 |
1 |
1 |
269 |
1 |
1 |
270 |
1 |
1 |
271 |
0 |
1 |
272 |
1 |
1 |
274 |
1 |
1 |
|
|
|
MISSING_ELSE |
287 |
1 |
1 |
307 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
319 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
338 |
1 |
1 |
341 |
1 |
1 |
345 |
1 |
1 |
349 |
1 |
1 |
353 |
1 |
1 |
358 |
1 |
1 |
372 |
1 |
1 |
394 |
1 |
1 |
420 |
1 |
1 |
421 |
1 |
1 |
422 |
1 |
1 |
423 |
1 |
1 |
424 |
1 |
1 |
425 |
1 |
1 |
431 |
1 |
1 |
Cond Coverage for Module :
kmac_core
| Total | Covered | Percent |
Conditions | 28 | 26 | 92.86 |
Logical | 28 | 26 | 92.86 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 180
EXPRESSION (kmac_en_i && start_i)
----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T13,T14 |
1 | 1 | Covered | T2,T13,T14 |
LINE 207
EXPRESSION (process_i || process_latched)
----1---- -------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T2,T13,T14 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T2,T13,T14 |
LINE 251
EXPRESSION (en_kmac_datapath ? kmac_valid : fifo_valid_i)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T13,T14 |
LINE 252
EXPRESSION (en_kmac_datapath ? kmac_data : fifo_data_i)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T13,T14 |
LINE 253
EXPRESSION (en_kmac_datapath ? kmac_strb : fifo_strb_i)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T13,T14 |
LINE 254
EXPRESSION (en_kmac_datapath ? 1'b0 : msg_ready_i)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T13,T14 |
LINE 258
EXPRESSION (en_key_write ? '1 : '0)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T13,T14 |
LINE 260
EXPRESSION (en_key_write ? key_sliced : ('{(*adjust*)default:'0}))
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T13,T14 |
LINE 265
EXPRESSION (kmac_en_i ? kmac_process : process_i)
----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T13,T14 |
LINE 270
EXPRESSION (process_i && ((!process_o)))
----1---- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Not Covered | |
LINE 394
EXPRESSION (kmac_valid & msg_ready_i)
-----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T13,T14 |
1 | 1 | Covered | T2,T13,T14 |
LINE 431
EXPRESSION (key_index == block_addr_limit)
---------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T13,T14 |
FSM Coverage for Module :
kmac_core
Summary for FSM :: st
| Total | Covered | Percent | |
States |
5 |
5 |
100.00 |
(Not included in score) |
Transitions |
8 |
8 |
100.00 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: st
states | Line No. | Covered | Tests |
StKey |
181 |
Covered |
T2,T13,T14 |
StKmacFlush |
208 |
Covered |
T2,T13,T14 |
StKmacIdle |
183 |
Covered |
T1,T2,T3 |
StKmacMsg |
194 |
Covered |
T2,T13,T14 |
StTerminalError |
241 |
Covered |
T4,T5,T6 |
transitions | Line No. | Covered | Tests |
StKey->StKmacMsg |
194 |
Covered |
T2,T13,T14 |
StKey->StTerminalError |
241 |
Covered |
T5,T8,T84 |
StKmacFlush->StKmacIdle |
218 |
Covered |
T2,T13,T14 |
StKmacFlush->StTerminalError |
241 |
Covered |
T49,T86 |
StKmacIdle->StKey |
181 |
Covered |
T2,T13,T14 |
StKmacIdle->StTerminalError |
241 |
Covered |
T6,T34,T48 |
StKmacMsg->StKmacFlush |
208 |
Covered |
T2,T13,T14 |
StKmacMsg->StTerminalError |
241 |
Covered |
T4,T35,T87 |
Branch Coverage for Module :
kmac_core
| Line No. | Total | Covered | Percent |
Branches |
|
50 |
46 |
92.00 |
TERNARY |
251 |
2 |
2 |
100.00 |
TERNARY |
252 |
2 |
2 |
100.00 |
TERNARY |
253 |
2 |
2 |
100.00 |
TERNARY |
254 |
2 |
2 |
100.00 |
TERNARY |
258 |
2 |
2 |
100.00 |
TERNARY |
260 |
2 |
2 |
100.00 |
TERNARY |
265 |
2 |
2 |
100.00 |
IF |
161 |
2 |
2 |
100.00 |
CASE |
178 |
10 |
10 |
100.00 |
IF |
240 |
2 |
2 |
100.00 |
IF |
268 |
4 |
3 |
75.00 |
CASE |
307 |
6 |
5 |
83.33 |
CASE |
420 |
6 |
5 |
83.33 |
CASE |
338 |
6 |
5 |
83.33 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 251 (en_kmac_datapath) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T13,T14 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 252 (en_kmac_datapath) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T13,T14 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 253 (en_kmac_datapath) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T13,T14 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 254 (en_kmac_datapath) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T13,T14 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 258 (en_key_write) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T13,T14 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 260 (en_key_write) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T13,T14 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 265 (kmac_en_i) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T13,T14 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 161 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 178 case (st)
-2-: 180 if ((kmac_en_i && start_i))
-3-: 193 if (sent_blocksize)
-4-: 207 if ((process_i || process_latched))
-5-: 217 if (prim_mubi_pkg::mubi4_test_true_strict(done_i))
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
StKmacIdle |
1 |
- |
- |
- |
Covered |
T2,T13,T14 |
StKmacIdle |
0 |
- |
- |
- |
Covered |
T1,T2,T3 |
StKey |
- |
1 |
- |
- |
Covered |
T2,T13,T14 |
StKey |
- |
0 |
- |
- |
Covered |
T2,T13,T14 |
StKmacMsg |
- |
- |
1 |
- |
Covered |
T2,T13,T14 |
StKmacMsg |
- |
- |
0 |
- |
Covered |
T2,T13,T14 |
StKmacFlush |
- |
- |
- |
1 |
Covered |
T2,T13,T14 |
StKmacFlush |
- |
- |
- |
0 |
Covered |
T2,T13,T14 |
StTerminalError |
- |
- |
- |
- |
Covered |
T4,T5,T6 |
default |
- |
- |
- |
- |
Covered |
T10,T11,T12 |
LineNo. Expression
-1-: 240 if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 268 if ((!rst_ni))
-2-: 270 if ((process_i && (!process_o)))
-3-: 272 if ((process_o || prim_mubi_pkg::mubi4_test_true_strict(done_i)))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 307 case (key_len_i)
Branches:
-1- | Status | Tests |
Key128 |
Covered |
T1,T2,T3 |
Key192 |
Covered |
T1,T2,T3 |
Key256 |
Covered |
T1,T2,T3 |
Key384 |
Covered |
T1,T2,T3 |
Key512 |
Covered |
T1,T2,T3 |
default |
Not Covered |
|
LineNo. Expression
-1-: 420 case (strength_i)
Branches:
-1- | Status | Tests |
L128 |
Covered |
T1,T2,T3 |
L224 |
Covered |
T13,T16,T27 |
L256 |
Covered |
T1,T2,T3 |
L384 |
Covered |
T1,T3,T13 |
L512 |
Covered |
T14,T17,T27 |
default |
Not Covered |
|
LineNo. Expression
-1-: 338 case (key_len_i)
Branches:
-1- | Status | Tests |
Key128 |
Covered |
T1,T2,T3 |
Key192 |
Covered |
T1,T2,T3 |
Key256 |
Covered |
T1,T2,T3 |
Key384 |
Covered |
T1,T2,T3 |
Key512 |
Covered |
T1,T2,T3 |
default |
Not Covered |
|
Assert Coverage for Module :
kmac_core
Assertion Details
AckOnlyInMessageState_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
7659625 |
0 |
0 |
T2 |
122556 |
229 |
0 |
0 |
T3 |
604515 |
0 |
0 |
0 |
T13 |
130244 |
4924 |
0 |
0 |
T14 |
549015 |
6427 |
0 |
0 |
T15 |
506825 |
0 |
0 |
0 |
T16 |
831044 |
0 |
0 |
0 |
T17 |
945171 |
0 |
0 |
0 |
T18 |
724619 |
1876 |
0 |
0 |
T19 |
15665 |
109 |
0 |
0 |
T27 |
0 |
2878 |
0 |
0 |
T37 |
257059 |
0 |
0 |
0 |
T58 |
0 |
12805 |
0 |
0 |
T59 |
0 |
109 |
0 |
0 |
T61 |
0 |
109 |
0 |
0 |
T62 |
0 |
109 |
0 |
0 |
KeyDataStableWhenValid_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
367312683 |
0 |
0 |
T2 |
122556 |
34449 |
0 |
0 |
T3 |
604515 |
0 |
0 |
0 |
T4 |
0 |
194 |
0 |
0 |
T13 |
130244 |
717506 |
0 |
0 |
T14 |
549015 |
259379 |
0 |
0 |
T15 |
506825 |
0 |
0 |
0 |
T16 |
831044 |
0 |
0 |
0 |
T17 |
945171 |
0 |
0 |
0 |
T18 |
724619 |
292806 |
0 |
0 |
T19 |
15665 |
11600 |
0 |
0 |
T27 |
0 |
342224 |
0 |
0 |
T37 |
257059 |
0 |
0 |
0 |
T58 |
0 |
335302 |
0 |
0 |
T59 |
0 |
4497 |
0 |
0 |
T61 |
0 |
4336 |
0 |
0 |
KeyLengthStableWhenValid_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
367312683 |
0 |
0 |
T2 |
122556 |
34449 |
0 |
0 |
T3 |
604515 |
0 |
0 |
0 |
T4 |
0 |
194 |
0 |
0 |
T13 |
130244 |
717506 |
0 |
0 |
T14 |
549015 |
259379 |
0 |
0 |
T15 |
506825 |
0 |
0 |
0 |
T16 |
831044 |
0 |
0 |
0 |
T17 |
945171 |
0 |
0 |
0 |
T18 |
724619 |
292806 |
0 |
0 |
T19 |
15665 |
11600 |
0 |
0 |
T27 |
0 |
342224 |
0 |
0 |
T37 |
257059 |
0 |
0 |
0 |
T58 |
0 |
335302 |
0 |
0 |
T59 |
0 |
4497 |
0 |
0 |
T61 |
0 |
4336 |
0 |
0 |
KmacEnStable_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
21421 |
0 |
0 |
T2 |
122556 |
6 |
0 |
0 |
T3 |
604515 |
0 |
0 |
0 |
T4 |
0 |
1 |
0 |
0 |
T13 |
130244 |
53 |
0 |
0 |
T14 |
549015 |
90 |
0 |
0 |
T15 |
506825 |
0 |
0 |
0 |
T16 |
831044 |
0 |
0 |
0 |
T17 |
945171 |
0 |
0 |
0 |
T18 |
724619 |
34 |
0 |
0 |
T19 |
15665 |
1 |
0 |
0 |
T20 |
0 |
1 |
0 |
0 |
T27 |
0 |
36 |
0 |
0 |
T37 |
257059 |
0 |
0 |
0 |
T58 |
0 |
9 |
0 |
0 |
T59 |
0 |
1 |
0 |
0 |
MaxKeyLenMatchToKey512_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1024 |
1024 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
ModeStable_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
32633 |
0 |
0 |
T2 |
122556 |
7 |
0 |
0 |
T3 |
604515 |
0 |
0 |
0 |
T13 |
130244 |
98 |
0 |
0 |
T14 |
549015 |
163 |
0 |
0 |
T15 |
506825 |
1 |
0 |
0 |
T16 |
831044 |
0 |
0 |
0 |
T17 |
945171 |
0 |
0 |
0 |
T18 |
724619 |
77 |
0 |
0 |
T19 |
15665 |
1 |
0 |
0 |
T20 |
0 |
1 |
0 |
0 |
T27 |
0 |
43 |
0 |
0 |
T37 |
257059 |
1 |
0 |
0 |
T58 |
0 |
9 |
0 |
0 |
ProcessLatchedCleared_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
0 |
0 |
0 |
StrengthStable_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
38834 |
0 |
0 |
T1 |
700217 |
2 |
0 |
0 |
T2 |
122556 |
6 |
0 |
0 |
T3 |
604515 |
2 |
0 |
0 |
T13 |
130244 |
84 |
0 |
0 |
T14 |
549015 |
191 |
0 |
0 |
T15 |
506825 |
1 |
0 |
0 |
T16 |
831044 |
2 |
0 |
0 |
T17 |
945171 |
2 |
0 |
0 |
T18 |
724619 |
85 |
0 |
0 |
T19 |
15665 |
2 |
0 |
0 |
u_state_regs_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
700217 |
700209 |
0 |
0 |
T2 |
122556 |
122460 |
0 |
0 |
T3 |
604515 |
604509 |
0 |
0 |
T13 |
130244 |
130235 |
0 |
0 |
T14 |
549015 |
548750 |
0 |
0 |
T15 |
506825 |
506815 |
0 |
0 |
T16 |
831044 |
831036 |
0 |
0 |
T17 |
945171 |
945107 |
0 |
0 |
T18 |
724619 |
724388 |
0 |
0 |
T19 |
15665 |
15592 |
0 |
0 |