Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	31989	0	0
entropy_period_rd_A	2147483647	2457	0	0
intr_enable_rd_A	2147483647	3227	0	0
prefix_0_rd_A	2147483647	2373	0	0
prefix_10_rd_A	2147483647	2206	0	0
prefix_1_rd_A	2147483647	2276	0	0
prefix_2_rd_A	2147483647	2255	0	0
prefix_3_rd_A	2147483647	2222	0	0
prefix_4_rd_A	2147483647	2255	0	0
prefix_5_rd_A	2147483647	2246	0	0
prefix_6_rd_A	2147483647	2208	0	0
prefix_7_rd_A	2147483647	2303	0	0
prefix_8_rd_A	2147483647	2342	0	0
prefix_9_rd_A	2147483647	2228	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	31989	0	0
T31	277085	29069	0	0
T46	0	70	0	0
T47	0	1	0	0
T106	0	46	0	0
T109	0	1	0	0
T110	0	213	0	0
T120	0	93	0	0
T121	0	40	0	0
T125	0	7	0	0
T126	0	1	0	0
T127	3757	0	0	0
T128	60040	0	0	0
T129	16748	0	0	0
T130	265959	0	0	0
T131	1413	0	0	0
T132	382553	0	0	0
T133	711651	0	0	0
T134	478524	0	0	0
T135	924	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2457	0	0
T88	6580	36	0	0
T89	6425	27	0	0
T101	2638	8	0	0
T107	7309	41	0	0
T112	12514	60	0	0
T125	8224	25	0	0
T147	1715	10	0	0
T148	3007	2	0	0
T149	11152	13	0	0
T150	143599	215	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3227	0	0
T88	6580	43	0	0
T89	6425	51	0	0
T101	2638	11	0	0
T116	951	2	0	0
T118	1497	23	0	0
T120	7173	2	0	0
T125	8224	15	0	0
T147	1715	7	0	0
T151	1149	27	0	0
T152	995	15	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2373	0	0
T88	6580	30	0	0
T89	6425	30	0	0
T101	2638	10	0	0
T107	7309	29	0	0
T112	12514	47	0	0
T125	8224	15	0	0
T147	1715	1	0	0
T148	3007	6	0	0
T149	11152	11	0	0
T150	143599	412	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2206	0	0
T88	6580	8	0	0
T89	6425	19	0	0
T101	2638	3	0	0
T107	7309	30	0	0
T112	12514	31	0	0
T125	8224	21	0	0
T147	1715	5	0	0
T149	11152	5	0	0
T150	143599	480	0	0
T153	26403	80	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2276	0	0
T88	6580	30	0	0
T89	6425	18	0	0
T101	2638	10	0	0
T107	7309	22	0	0
T112	12514	20	0	0
T125	8224	20	0	0
T147	1715	9	0	0
T148	3007	6	0	0
T149	11152	40	0	0
T150	143599	452	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2255	0	0
T88	6580	28	0	0
T89	6425	24	0	0
T101	2638	5	0	0
T107	7309	35	0	0
T112	12514	54	0	0
T125	8224	23	0	0
T147	1715	6	0	0
T148	3007	6	0	0
T149	11152	15	0	0
T150	143599	442	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2222	0	0
T88	6580	26	0	0
T89	6425	26	0	0
T101	2638	4	0	0
T107	7309	35	0	0
T112	12514	52	0	0
T125	8224	14	0	0
T147	1715	2	0	0
T148	3007	9	0	0
T149	11152	12	0	0
T150	143599	414	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2255	0	0
T88	6580	9	0	0
T89	6425	35	0	0
T101	2638	10	0	0
T107	7309	36	0	0
T112	12514	38	0	0
T125	8224	17	0	0
T148	3007	6	0	0
T149	11152	19	0	0
T150	143599	445	0	0
T153	26403	68	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2246	0	0
T88	6580	33	0	0
T89	6425	25	0	0
T101	2638	11	0	0
T107	7309	21	0	0
T112	12514	30	0	0
T125	8224	17	0	0
T147	1715	2	0	0
T148	3007	8	0	0
T149	11152	32	0	0
T150	143599	404	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2208	0	0
T88	6580	31	0	0
T89	6425	30	0	0
T101	2638	11	0	0
T107	7309	42	0	0
T112	12514	39	0	0
T125	8224	21	0	0
T147	1715	5	0	0
T148	3007	5	0	0
T149	11152	41	0	0
T150	143599	397	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2303	0	0
T88	6580	32	0	0
T89	6425	35	0	0
T101	2638	8	0	0
T107	7309	40	0	0
T112	12514	31	0	0
T125	8224	15	0	0
T147	1715	9	0	0
T148	3007	6	0	0
T149	11152	23	0	0
T150	143599	439	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2342	0	0
T88	6580	22	0	0
T89	6425	45	0	0
T101	2638	9	0	0
T107	7309	39	0	0
T112	12514	33	0	0
T125	8224	11	0	0
T147	1715	5	0	0
T148	3007	5	0	0
T149	11152	34	0	0
T150	143599	440	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2228	0	0
T88	6580	45	0	0
T89	6425	27	0	0
T101	2638	6	0	0
T107	7309	28	0	0
T112	12514	39	0	0
T125	8224	29	0	0
T148	3007	3	0	0
T149	11152	11	0	0
T150	143599	402	0	0
T153	26403	94	0	0