Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	251891672	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

197317415

1

T1

887695

T2

888901

T3

887569

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	237189572	1			T1	109748		T2	109234		T3	111240
values[0x0]	101902860	1			T1	445720		T2	442002		T3	450860
values[0x1]	110116655	1			T1	479769		T2	472921		T3	490107

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	196402149	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

252806938

1

T1

113549

T2

113129

T3

114480

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1408448	1			T1	7996		T2	7797		T3	7004
valid_sources[0x01]	1342720	1			T1	7857		T2	8213		T3	7656
valid_sources[0x02]	1339716	1			T1	7826		T2	8127		T3	7697
valid_sources[0x03]	1341360	1			T1	8008		T2	7829		T3	7793
valid_sources[0x04]	1349848	1			T1	7824		T2	7573		T3	8077
valid_sources[0x05]	3113784	1			T1	7840		T2	7786		T3	8618
valid_sources[0x06]	1351822	1			T1	7802		T2	7935		T3	8595
valid_sources[0x07]	1509847	1			T1	7944		T2	7809		T3	8369
valid_sources[0x08]	1342409	1			T1	7956		T2	7700		T3	8172
valid_sources[0x09]	2001586	1			T1	7917		T2	7338		T3	7250
valid_sources[0x0a]	3108291	1			T1	7813		T2	7841		T3	8756
valid_sources[0x0b]	1342130	1			T1	7935		T2	7548		T3	7929
valid_sources[0x0c]	1355703	1			T1	7878		T2	7829		T3	7587
valid_sources[0x0d]	1807630	1			T1	8035		T2	7545		T3	7672
valid_sources[0x0e]	1521482	1			T1	7762		T2	7830		T3	7440
valid_sources[0x0f]	1336770	1			T1	8005		T2	7726		T3	8163
valid_sources[0x10]	1341576	1			T1	7994		T2	7623		T3	7482
valid_sources[0x11]	1343466	1			T1	7684		T2	7704		T3	6910
valid_sources[0x12]	1340286	1			T1	7831		T2	7878		T3	8171
valid_sources[0x13]	1361398	1			T1	7945		T2	8004		T3	8185
valid_sources[0x14]	1343406	1			T1	7953		T2	7573		T3	7850
valid_sources[0x15]	5719845	1			T1	7961		T2	7910		T3	7739
valid_sources[0x16]	1373877	1			T1	8001		T2	8012		T3	8511
valid_sources[0x17]	1408362	1			T1	7915		T2	7461		T3	8122
valid_sources[0x18]	1995141	1			T1	7784		T2	7609		T3	7584
valid_sources[0x19]	1351684	1			T1	7922		T2	7744		T3	8874
valid_sources[0x1a]	3345100	1			T1	7806		T2	7956		T3	7204
valid_sources[0x1b]	1477141	1			T1	7799		T2	7776		T3	8156
valid_sources[0x1c]	1340577	1			T1	7958		T2	7880		T3	7796
valid_sources[0x1d]	1345948	1			T1	7700		T2	7753		T3	8202
valid_sources[0x1e]	1391866	1			T1	7898		T2	7808		T3	7872
valid_sources[0x1f]	1810350	1			T1	7972		T2	7900		T3	8463
valid_sources[0x20]	1416395	1			T1	7920		T2	7863		T3	8607
valid_sources[0x21]	1359360	1			T1	7861		T2	7579		T3	8754
valid_sources[0x22]	3777039	1			T1	7993		T2	8101		T3	7296
valid_sources[0x23]	1365968	1			T1	7958		T2	7944		T3	7260
valid_sources[0x24]	1344838	1			T1	7849		T2	7639		T3	7349
valid_sources[0x25]	1361833	1			T1	7884		T2	7522		T3	8039
valid_sources[0x26]	1347495	1			T1	7875		T2	7663		T3	8352
valid_sources[0x27]	1339904	1			T1	7888		T2	7824		T3	8159
valid_sources[0x28]	1339449	1			T1	8011		T2	7900		T3	7673
valid_sources[0x29]	1346114	1			T1	7760		T2	7377		T3	8804
valid_sources[0x2a]	1337430	1			T1	7995		T2	7547		T3	8060
valid_sources[0x2b]	1340703	1			T1	8073		T2	7832		T3	8405
valid_sources[0x2c]	2274807	1			T1	7989		T2	8131		T3	8556
valid_sources[0x2d]	1348491	1			T1	8033		T2	8028		T3	8451
valid_sources[0x2e]	2225957	1			T1	7954		T2	7734		T3	8758
valid_sources[0x2f]	1800128	1			T1	7911		T2	7697		T3	8269
valid_sources[0x30]	1345157	1			T1	7799		T2	7699		T3	8617
valid_sources[0x31]	2226645	1			T1	8025		T2	7874		T3	8581
valid_sources[0x32]	1376075	1			T1	7880		T2	7800		T3	8604
valid_sources[0x33]	1342103	1			T1	8010		T2	7812		T3	7775
valid_sources[0x34]	1998876	1			T1	7952		T2	7642		T3	7741
valid_sources[0x35]	1343560	1			T1	8023		T2	8038		T3	8101
valid_sources[0x36]	1345978	1			T1	7964		T2	8526		T3	8124
valid_sources[0x37]	1339340	1			T1	7988		T2	7548		T3	8520
valid_sources[0x38]	1344229	1			T1	7816		T2	7735		T3	7372
valid_sources[0x39]	2207407	1			T1	7860		T2	7643		T3	7304
valid_sources[0x3a]	1469834	1			T1	7893		T2	7998		T3	7769
valid_sources[0x3b]	1496630	1			T1	7877		T2	7514		T3	9003
valid_sources[0x3c]	1386255	1			T1	7993		T2	7805		T3	7542
valid_sources[0x3d]	1351528	1			T1	7839		T2	7627		T3	7716
valid_sources[0x3e]	1347032	1			T1	8122		T2	7678		T3	8420
valid_sources[0x3f]	1341844	1			T1	8016		T2	7957		T3	8910
valid_sources[0x40]	2549286	1			T1	7796		T2	8346		T3	8858
valid_sources[0x41]	1342004	1			T1	7955		T2	7583		T3	7856
valid_sources[0x42]	1337571	1			T1	7796		T2	7500		T3	8977
valid_sources[0x43]	1341537	1			T1	7879		T2	7877		T3	7781
valid_sources[0x44]	1338907	1			T1	7973		T2	8112		T3	9035
valid_sources[0x45]	1339870	1			T1	8041		T2	7949		T3	7369
valid_sources[0x46]	1345037	1			T1	7933		T2	7978		T3	8053
valid_sources[0x47]	3738670	1			T1	7871		T2	7901		T3	7620
valid_sources[0x48]	2000588	1			T1	7864		T2	7796		T3	7914
valid_sources[0x49]	1338182	1			T1	8011		T2	7911		T3	7795
valid_sources[0x4a]	1361279	1			T1	7790		T2	8103		T3	7015
valid_sources[0x4b]	5255336	1			T1	7906		T2	7597		T3	7639
valid_sources[0x4c]	1346963	1			T1	7878		T2	7697		T3	7360
valid_sources[0x4d]	1344970	1			T1	7939		T2	7679		T3	8014
valid_sources[0x4e]	1338735	1			T1	7860		T2	7796		T3	7366
valid_sources[0x4f]	1343141	1			T1	7804		T2	7668		T3	8360
valid_sources[0x50]	1411983	1			T1	7778		T2	7417		T3	8632
valid_sources[0x51]	1342416	1			T1	7948		T2	7681		T3	7804
valid_sources[0x52]	1345487	1			T1	7974		T2	7847		T3	8086
valid_sources[0x53]	1344369	1			T1	7650		T2	7854		T3	8310
valid_sources[0x54]	1343390	1			T1	7897		T2	8032		T3	8778
valid_sources[0x55]	1341601	1			T1	7893		T2	7862		T3	7572
valid_sources[0x56]	1340567	1			T1	7805		T2	7658		T3	7822
valid_sources[0x57]	1344018	1			T1	7965		T2	7945		T3	7681
valid_sources[0x58]	1869616	1			T1	7757		T2	7524		T3	7108
valid_sources[0x59]	3390262	1			T1	7733		T2	7768		T3	7179
valid_sources[0x5a]	1810808	1			T1	8046		T2	7921		T3	7694
valid_sources[0x5b]	1340204	1			T1	7730		T2	7715		T3	7695
valid_sources[0x5c]	1342043	1			T1	7772		T2	7628		T3	8131
valid_sources[0x5d]	1530110	1			T1	7870		T2	7930		T3	8864
valid_sources[0x5e]	1368676	1			T1	7842		T2	8153		T3	8421
valid_sources[0x5f]	2726088	1			T1	8001		T2	8089		T3	7256
valid_sources[0x60]	1340930	1			T1	7905		T2	7281		T3	8342
valid_sources[0x61]	1342491	1			T1	7684		T2	8251		T3	7787
valid_sources[0x62]	1348698	1			T1	7940		T2	7839		T3	7491
valid_sources[0x63]	1348479	1			T1	7909		T2	7866		T3	8179
valid_sources[0x64]	1347211	1			T1	7852		T2	7814		T3	8584
valid_sources[0x65]	1343624	1			T1	7913		T2	7868		T3	5921
valid_sources[0x66]	1347700	1			T1	7919		T2	8138		T3	8450
valid_sources[0x67]	2246139	1			T1	8057		T2	7820		T3	8318
valid_sources[0x68]	1340499	1			T1	7775		T2	7953		T3	7812
valid_sources[0x69]	2211540	1			T1	8116		T2	7935		T3	8340
valid_sources[0x6a]	1339845	1			T1	7865		T2	7974		T3	8340
valid_sources[0x6b]	1387575	1			T1	7923		T2	7581		T3	8090
valid_sources[0x6c]	1339974	1			T1	7851		T2	7902		T3	7950
valid_sources[0x6d]	1347323	1			T1	7901		T2	7777		T3	8511
valid_sources[0x6e]	1805568	1			T1	7846		T2	7585		T3	8592
valid_sources[0x6f]	1340831	1			T1	8011		T2	7674		T3	8537
valid_sources[0x70]	1345314	1			T1	7849		T2	8052		T3	8115
valid_sources[0x71]	1350801	1			T1	7748		T2	7706		T3	8227
valid_sources[0x72]	3783925	1			T1	8040		T2	7561		T3	8059
valid_sources[0x73]	2230529	1			T1	7783		T2	7489		T3	8579
valid_sources[0x74]	1464998	1			T1	7800		T2	7658		T3	8271
valid_sources[0x75]	1411442	1			T1	7914		T2	7954		T3	8960
valid_sources[0x76]	1339025	1			T1	7927		T2	7542		T3	8652
valid_sources[0x77]	1343266	1			T1	7987		T2	7776		T3	7026
valid_sources[0x78]	1345514	1			T1	7869		T2	7813		T3	8416
valid_sources[0x79]	1815930	1			T1	7800		T2	8057		T3	7732
valid_sources[0x7a]	1338895	1			T1	7781		T2	8237		T3	8996
valid_sources[0x7b]	1347545	1			T1	7891		T2	8266		T3	9406
valid_sources[0x7c]	1341149	1			T1	7917		T2	7713		T3	8546
valid_sources[0x7d]	1400921	1			T1	8014		T2	7842		T3	8571
valid_sources[0x7e]	1347826	1			T1	7868		T2	7825		T3	7601
valid_sources[0x7f]	1490022	1			T1	7849		T2	7412		T3	7888
valid_sources[0x80]	2281714	1			T1	7984		T2	7751		T3	8127

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

86027538

1

T1

416694

T2

414258

T3

420673

values[0x0]

all_enables

biggest_size

59889686

1

T1

255042

T2

256703

T3

253282

values[0x1]

all_enables

biggest_size

51400191

1

T1

215959

T2

217940

T3

213614