Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

252082181

1

T1

113527

T2

111836

T3

116580

full_word

197329313

1

T1

887695

T2

888901

T3

887569

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	449411204	1			T1	202297		T2	200727		T3	205337
auto[TlIntgErrCmd]	110	1			T115	3		T116	2		T117	11
auto[TlIntgErrData]	91	1			T115	4		T116	5		T117	5
auto[TlIntgErrBoth]	89	1			T115	3		T116	3		T117	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

237226419

1

T1

109748

T2

109234

T3

111240

auto[1]

212185075

1

T1

925489

T2

914923

T3

940967

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	151195772	1			T1	680789		T2	678089		T3	691732
auto[TlIntgErrNone]	partial	auto[1]	100886144	1			T1	454488		T2	440280		T3	474071
auto[TlIntgErrNone]	full_word	auto[0]	86030524	1			T1	416694		T2	414258		T3	420673
auto[TlIntgErrNone]	full_word	auto[1]	111298764	1			T1	471001		T2	474643		T3	466896
auto[TlIntgErrCmd]	partial	auto[0]	39	1			T115	1		T116	1		T117	5
auto[TlIntgErrCmd]	partial	auto[1]	64	1			T115	2		T116	1		T117	6
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T186	1		T188	2		T191	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T186	1		T192	1		-	-
auto[TlIntgErrData]	partial	auto[0]	43	1			T115	1		T116	4		T117	1
auto[TlIntgErrData]	partial	auto[1]	39	1			T115	3		T116	1		T117	4
auto[TlIntgErrData]	full_word	auto[0]	3	1			T188	1		T191	1		T190	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T191	2		T189	1		T193	1
auto[TlIntgErrBoth]	partial	auto[0]	29	1			T115	1		T116	1		T117	2
auto[TlIntgErrBoth]	partial	auto[1]	51	1			T115	2		T116	1		T117	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T116	1		T187	1		T189	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T187	1		T191	1		T194	1