Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	43597	0	0
entropy_period_rd_A	2147483647	1616	0	0
intr_enable_rd_A	2147483647	2380	0	0
prefix_0_rd_A	2147483647	1663	0	0
prefix_10_rd_A	2147483647	1579	0	0
prefix_1_rd_A	2147483647	1682	0	0
prefix_2_rd_A	2147483647	1581	0	0
prefix_3_rd_A	2147483647	1695	0	0
prefix_4_rd_A	2147483647	1716	0	0
prefix_5_rd_A	2147483647	1658	0	0
prefix_6_rd_A	2147483647	1907	0	0
prefix_7_rd_A	2147483647	1747	0	0
prefix_8_rd_A	2147483647	1691	0	0
prefix_9_rd_A	2147483647	1595	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	43597	0	0
T30	124574	17180	0	0
T52	0	23126	0	0
T53	0	311	0	0
T115	0	2	0	0
T118	0	260	0	0
T119	0	112	0	0
T123	0	273	0	0
T124	0	255	0	0
T126	0	6	0	0
T127	0	134	0	0
T128	930	0	0	0
T129	1516	0	0	0
T130	16901	0	0	0
T131	588967	0	0	0
T132	103469	0	0	0
T133	24017	0	0	0
T134	616324	0	0	0
T135	146368	0	0	0
T136	2055	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1616	0	0
T52	294392	66	0	0
T102	0	116	0	0
T125	0	25	0	0
T126	0	43	0	0
T149	0	14	0	0
T150	0	38	0	0
T151	0	5	0	0
T152	0	7	0	0
T153	0	68	0	0
T154	0	21	0	0
T155	169362	0	0	0
T156	104080	0	0	0
T157	241792	0	0	0
T158	78695	0	0	0
T159	458294	0	0	0
T160	131340	0	0	0
T161	981864	0	0	0
T162	25477	0	0	0
T163	750429	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2380	0	0
T52	294392	70	0	0
T102	0	216	0	0
T120	0	13	0	0
T126	0	34	0	0
T149	0	26	0	0
T150	0	56	0	0
T151	0	4	0	0
T152	0	25	0	0
T155	169362	0	0	0
T156	104080	0	0	0
T157	241792	0	0	0
T158	78695	0	0	0
T159	458294	0	0	0
T160	131340	0	0	0
T161	981864	0	0	0
T162	25477	0	0	0
T163	750429	0	0	0
T164	0	15	0	0
T165	0	9	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1663	0	0
T52	294392	30	0	0
T102	0	229	0	0
T125	0	29	0	0
T126	0	13	0	0
T149	0	9	0	0
T150	0	15	0	0
T151	0	3	0	0
T152	0	5	0	0
T153	0	40	0	0
T154	0	22	0	0
T155	169362	0	0	0
T156	104080	0	0	0
T157	241792	0	0	0
T158	78695	0	0	0
T159	458294	0	0	0
T160	131340	0	0	0
T161	981864	0	0	0
T162	25477	0	0	0
T163	750429	0	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1579	0	0
T52	294392	78	0	0
T102	0	197	0	0
T124	0	1	0	0
T125	0	16	0	0
T126	0	14	0	0
T149	0	10	0	0
T150	0	26	0	0
T152	0	7	0	0
T153	0	43	0	0
T154	0	18	0	0
T155	169362	0	0	0
T156	104080	0	0	0
T157	241792	0	0	0
T158	78695	0	0	0
T159	458294	0	0	0
T160	131340	0	0	0
T161	981864	0	0	0
T162	25477	0	0	0
T163	750429	0	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1682	0	0
T52	294392	81	0	0
T102	0	225	0	0
T125	0	23	0	0
T126	0	25	0	0
T149	0	3	0	0
T150	0	48	0	0
T151	0	6	0	0
T152	0	11	0	0
T153	0	28	0	0
T154	0	17	0	0
T155	169362	0	0	0
T156	104080	0	0	0
T157	241792	0	0	0
T158	78695	0	0	0
T159	458294	0	0	0
T160	131340	0	0	0
T161	981864	0	0	0
T162	25477	0	0	0
T163	750429	0	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1581	0	0
T52	294392	66	0	0
T102	0	212	0	0
T125	0	14	0	0
T126	0	7	0	0
T149	0	9	0	0
T150	0	59	0	0
T152	0	11	0	0
T153	0	38	0	0
T154	0	9	0	0
T155	169362	0	0	0
T156	104080	0	0	0
T157	241792	0	0	0
T158	78695	0	0	0
T159	458294	0	0	0
T160	131340	0	0	0
T161	981864	0	0	0
T162	25477	0	0	0
T163	750429	0	0	0
T166	0	22	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1695	0	0
T52	294392	93	0	0
T102	0	215	0	0
T125	0	23	0	0
T126	0	12	0	0
T149	0	2	0	0
T150	0	15	0	0
T151	0	6	0	0
T152	0	1	0	0
T153	0	52	0	0
T154	0	9	0	0
T155	169362	0	0	0
T156	104080	0	0	0
T157	241792	0	0	0
T158	78695	0	0	0
T159	458294	0	0	0
T160	131340	0	0	0
T161	981864	0	0	0
T162	25477	0	0	0
T163	750429	0	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1716	0	0
T52	294392	56	0	0
T102	0	214	0	0
T125	0	10	0	0
T126	0	21	0	0
T149	0	15	0	0
T150	0	29	0	0
T151	0	8	0	0
T152	0	4	0	0
T153	0	49	0	0
T154	0	14	0	0
T155	169362	0	0	0
T156	104080	0	0	0
T157	241792	0	0	0
T158	78695	0	0	0
T159	458294	0	0	0
T160	131340	0	0	0
T161	981864	0	0	0
T162	25477	0	0	0
T163	750429	0	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1658	0	0
T52	294392	52	0	0
T102	0	223	0	0
T125	0	26	0	0
T126	0	21	0	0
T149	0	6	0	0
T150	0	49	0	0
T151	0	2	0	0
T152	0	4	0	0
T153	0	28	0	0
T154	0	10	0	0
T155	169362	0	0	0
T156	104080	0	0	0
T157	241792	0	0	0
T158	78695	0	0	0
T159	458294	0	0	0
T160	131340	0	0	0
T161	981864	0	0	0
T162	25477	0	0	0
T163	750429	0	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1907	0	0
T52	294392	53	0	0
T102	0	222	0	0
T125	0	19	0	0
T126	0	14	0	0
T149	0	7	0	0
T150	0	61	0	0
T152	0	9	0	0
T153	0	89	0	0
T154	0	21	0	0
T155	169362	0	0	0
T156	104080	0	0	0
T157	241792	0	0	0
T158	78695	0	0	0
T159	458294	0	0	0
T160	131340	0	0	0
T161	981864	0	0	0
T162	25477	0	0	0
T163	750429	0	0	0
T166	0	14	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1747	0	0
T52	294392	66	0	0
T102	0	269	0	0
T125	0	13	0	0
T126	0	20	0	0
T149	0	14	0	0
T150	0	75	0	0
T151	0	6	0	0
T152	0	8	0	0
T153	0	45	0	0
T154	0	15	0	0
T155	169362	0	0	0
T156	104080	0	0	0
T157	241792	0	0	0
T158	78695	0	0	0
T159	458294	0	0	0
T160	131340	0	0	0
T161	981864	0	0	0
T162	25477	0	0	0
T163	750429	0	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1691	0	0
T52	294392	80	0	0
T102	0	232	0	0
T125	0	6	0	0
T126	0	22	0	0
T149	0	4	0	0
T150	0	54	0	0
T151	0	2	0	0
T152	0	6	0	0
T153	0	29	0	0
T154	0	6	0	0
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T156	104080	0	0	0
T157	241792	0	0	0
T158	78695	0	0	0
T159	458294	0	0	0
T160	131340	0	0	0
T161	981864	0	0	0
T162	25477	0	0	0
T163	750429	0	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1595	0	0
T52	294392	70	0	0
T102	0	224	0	0
T125	0	12	0	0
T126	0	12	0	0
T149	0	10	0	0
T150	0	39	0	0
T151	0	1	0	0
T152	0	15	0	0
T153	0	35	0	0
T154	0	10	0	0
T155	169362	0	0	0
T156	104080	0	0	0
T157	241792	0	0	0
T158	78695	0	0	0
T159	458294	0	0	0
T160	131340	0	0	0
T161	981864	0	0	0
T162	25477	0	0	0
T163	750429	0	0	0