SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
push_pull_agent_pkg.uvm_test_top.env.m_kmac_app_agent[0].m_data_push_agent.cov::m_valid_ready_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
push_pull_agent_pkg.uvm_test_top.env.m_kmac_app_agent[1].m_data_push_agent.cov::m_valid_ready_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
push_pull_agent_pkg.uvm_test_top.env.m_kmac_app_agent[2].m_data_push_agent.cov::m_valid_ready_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 4 | 0 | 4 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_valid_ready | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 4 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 4 | 0 | 4 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_valid_ready | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 4 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 4 | 0 | 4 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_valid_ready | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 51386 | 1 | T12 | 379 | T16 | 435 | T18 | 1 | ||||
auto[1] | 16106 | 1 | T12 | 8 | T16 | 9 | T4 | 3 | ||||
auto[2] | 274410 | 1 | T12 | 1247 | T16 | 1549 | T18 | 47 | ||||
auto[3] | 290265 | 1 | T12 | 1258 | T16 | 1561 | T4 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 22426 | 1 | T12 | 98 | T16 | 153 | T26 | 346 | ||||
auto[1] | 8955 | 1 | T12 | 2 | T16 | 4 | T4 | 1 | ||||
auto[2] | 119845 | 1 | T12 | 323 | T16 | 538 | T26 | 1178 | ||||
auto[3] | 128241 | 1 | T12 | 327 | T16 | 545 | T26 | 1188 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 26331 | 1 | T12 | 9 | T16 | 259 | T26 | 469 | ||||
auto[1] | 7449 | 1 | T12 | 2 | T16 | 7 | T4 | 1 | ||||
auto[2] | 134019 | 1 | T12 | 48 | T16 | 921 | T26 | 1669 | ||||
auto[3] | 140977 | 1 | T12 | 50 | T16 | 929 | T26 | 1683 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |