Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 254593674 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 199063587 1 T1 101267 T2 103260 T3 359134



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 239503226 1 T1 107245 T2 110903 T3 462755
values[0x0] 102958849 1 T1 24128 T2 26148 T3 213715
values[0x1] 111195186 1 T1 25927 T2 28602 T3 230179



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 198585639 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 255071622 1 T1 113686 T2 117325 T3 477865



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 1414294 1 T1 30 T2 40 T3 3490
valid_sources[0x01] 1566425 1 T1 33 T2 45 T3 3463
valid_sources[0x02] 1406626 1 T1 51 T2 39 T3 3601
valid_sources[0x03] 1503012 1 T1 32 T2 54 T3 3511
valid_sources[0x04] 1512861 1 T1 33 T2 31 T3 3648
valid_sources[0x05] 1413983 1 T1 29 T2 45 T3 3457
valid_sources[0x06] 2148868 1 T1 44 T2 48 T3 3515
valid_sources[0x07] 1454729 1 T1 50 T2 39 T3 3515
valid_sources[0x08] 3972942 1 T1 33 T2 45 T3 3555
valid_sources[0x09] 1411972 1 T1 37 T2 46 T3 3702
valid_sources[0x0a] 1551928 1 T1 53 T2 34 T3 3601
valid_sources[0x0b] 1405681 1 T1 41 T2 42 T3 3536
valid_sources[0x0c] 1475854 1 T1 40 T2 40 T3 3499
valid_sources[0x0d] 1583994 1 T1 32 T2 47 T3 3535
valid_sources[0x0e] 3795652 1 T1 24 T2 49 T3 3666
valid_sources[0x0f] 1417991 1 T1 32 T2 30 T3 3575
valid_sources[0x10] 3439173 1 T1 46 T2 50 T3 3703
valid_sources[0x11] 1511529 1 T1 41 T2 50 T3 3508
valid_sources[0x12] 1565117 1 T1 34 T2 39 T3 3483
valid_sources[0x13] 1423506 1 T1 40 T2 48 T3 3598
valid_sources[0x14] 3667066 1 T1 47 T2 30 T3 3545
valid_sources[0x15] 3821865 1 T1 38 T2 35 T3 3418
valid_sources[0x16] 3832136 1 T1 33 T2 44 T3 3588
valid_sources[0x17] 1423058 1 T1 39 T2 46 T3 3576
valid_sources[0x18] 1410815 1 T1 40 T2 48 T3 3663
valid_sources[0x19] 1410120 1 T1 28 T2 45 T3 3705
valid_sources[0x1a] 3455405 1 T1 48 T2 48 T3 3592
valid_sources[0x1b] 1419368 1 T1 41 T2 38 T3 3404
valid_sources[0x1c] 1424695 1 T1 42 T2 53 T3 3447
valid_sources[0x1d] 1434593 1 T1 41 T2 45 T3 3604
valid_sources[0x1e] 1414040 1 T1 36 T2 38 T3 3459
valid_sources[0x1f] 1417800 1 T1 49 T2 45 T3 3515
valid_sources[0x20] 1405539 1 T1 46 T2 47 T3 3537
valid_sources[0x21] 1844664 1 T1 41 T2 35 T3 3432
valid_sources[0x22] 1406039 1 T1 47 T2 34 T3 3670
valid_sources[0x23] 1410035 1 T1 46 T2 39 T3 3585
valid_sources[0x24] 2349667 1 T1 26 T2 33 T3 3530
valid_sources[0x25] 1411194 1 T1 34 T2 35 T3 3562
valid_sources[0x26] 1416458 1 T1 51 T2 41 T3 3488
valid_sources[0x27] 1417820 1 T1 40 T2 36 T3 3507
valid_sources[0x28] 1433763 1 T1 46 T2 47 T3 3422
valid_sources[0x29] 1407516 1 T1 40 T2 33 T3 3550
valid_sources[0x2a] 1436557 1 T1 39 T2 37 T3 3467
valid_sources[0x2b] 1416765 1 T1 48 T2 53 T3 3489
valid_sources[0x2c] 1414718 1 T1 54 T2 44 T3 3710
valid_sources[0x2d] 1473776 1 T1 56 T2 43 T3 3440
valid_sources[0x2e] 1428159 1 T1 52 T2 41 T3 3400
valid_sources[0x2f] 1422202 1 T1 44 T2 44 T3 3520
valid_sources[0x30] 1418474 1 T1 49 T2 60 T3 3505
valid_sources[0x31] 1414308 1 T1 37 T2 48 T3 3466
valid_sources[0x32] 2257248 1 T1 59 T2 37 T3 3719
valid_sources[0x33] 1405966 1 T1 50 T2 48 T3 3588
valid_sources[0x34] 1419189 1 T1 40 T2 48 T3 3411
valid_sources[0x35] 1418033 1 T1 42 T2 40 T3 3558
valid_sources[0x36] 1415547 1 T1 42 T2 44 T3 3604
valid_sources[0x37] 2470240 1 T1 34 T2 35 T3 3611
valid_sources[0x38] 1407898 1 T1 44 T2 50 T3 3547
valid_sources[0x39] 1416952 1 T1 44 T2 43 T3 3474
valid_sources[0x3a] 5130813 1 T1 43 T2 40 T3 3582
valid_sources[0x3b] 1414737 1 T1 32 T2 50 T3 3361
valid_sources[0x3c] 2585835 1 T1 43 T2 46 T3 3467
valid_sources[0x3d] 1426613 1 T1 55 T2 66 T3 3647
valid_sources[0x3e] 1416828 1 T1 51 T2 46 T3 3682
valid_sources[0x3f] 1415092 1 T1 46 T2 50 T3 3403
valid_sources[0x40] 1415263 1 T1 39 T2 40 T3 3621
valid_sources[0x41] 3464984 1 T1 38 T2 42 T3 3425
valid_sources[0x42] 1416450 1 T1 38 T2 43 T3 3499
valid_sources[0x43] 2391108 1 T1 35 T2 49 T3 3532
valid_sources[0x44] 2069164 1 T1 38 T2 54 T3 3479
valid_sources[0x45] 1414286 1 T1 39 T2 38 T3 3664
valid_sources[0x46] 4872796 1 T1 39 T2 52 T3 3391
valid_sources[0x47] 2757394 1 T1 52 T2 31 T3 3475
valid_sources[0x48] 1416538 1 T1 41 T2 44 T3 3648
valid_sources[0x49] 1403468 1 T1 45 T2 41 T3 3621
valid_sources[0x4a] 2082513 1 T1 52 T2 37 T3 3425
valid_sources[0x4b] 2305925 1 T1 32 T2 35 T3 3616
valid_sources[0x4c] 1457762 1 T1 51 T2 48 T3 3566
valid_sources[0x4d] 1580500 1 T1 44 T2 48 T3 3429
valid_sources[0x4e] 1414911 1 T1 32 T2 42 T3 3507
valid_sources[0x4f] 1406571 1 T1 43 T2 42 T3 3632
valid_sources[0x50] 1412593 1 T1 37 T2 50 T3 3613
valid_sources[0x51] 1410975 1 T1 28 T2 52 T3 3540
valid_sources[0x52] 1418962 1 T1 37 T2 51 T3 3523
valid_sources[0x53] 2339339 1 T1 49 T2 47 T3 3460
valid_sources[0x54] 1424617 1 T1 48 T2 35 T3 3530
valid_sources[0x55] 1423489 1 T1 41 T2 44 T3 3595
valid_sources[0x56] 2293198 1 T1 46 T2 36 T3 3561
valid_sources[0x57] 1445293 1 T1 27 T2 46 T3 3524
valid_sources[0x58] 1442031 1 T1 37 T2 45 T3 3513
valid_sources[0x59] 1416694 1 T1 56 T2 57 T3 3657
valid_sources[0x5a] 1414850 1 T1 36 T2 38 T3 3488
valid_sources[0x5b] 1414568 1 T1 39 T2 36 T3 3568
valid_sources[0x5c] 1417697 1 T1 31 T2 33 T3 3452
valid_sources[0x5d] 2110530 1 T1 37 T2 46 T3 3585
valid_sources[0x5e] 2445113 1 T1 34 T2 35 T3 3453
valid_sources[0x5f] 2326505 1 T1 51 T2 44 T3 3567
valid_sources[0x60] 1451245 1 T1 36 T2 42 T3 3596
valid_sources[0x61] 1414556 1 T1 33 T2 39 T3 3361
valid_sources[0x62] 1416390 1 T1 43 T2 49 T3 3508
valid_sources[0x63] 1406696 1 T1 44 T2 40 T3 3503
valid_sources[0x64] 1450273 1 T1 43 T2 41 T3 3657
valid_sources[0x65] 1504841 1 T1 39 T2 48 T3 3600
valid_sources[0x66] 1417098 1 T1 33 T2 42 T3 3617
valid_sources[0x67] 4956855 1 T1 45 T2 46 T3 3448
valid_sources[0x68] 1493157 1 T1 53 T2 44 T3 3552
valid_sources[0x69] 1412752 1 T1 41 T2 53 T3 3398
valid_sources[0x6a] 1542879 1 T1 33 T2 48 T3 3605
valid_sources[0x6b] 1422005 1 T1 44 T2 31 T3 3489
valid_sources[0x6c] 2506087 1 T1 45 T2 36 T3 3540
valid_sources[0x6d] 2320044 1 T1 40 T2 38 T3 3545
valid_sources[0x6e] 2433344 1 T1 36 T2 53 T3 3466
valid_sources[0x6f] 1408657 1 T1 31 T2 52 T3 3693
valid_sources[0x70] 1415422 1 T1 42 T2 41 T3 3548
valid_sources[0x71] 1407743 1 T1 35 T2 41 T3 3592
valid_sources[0x72] 1429438 1 T1 33 T2 49 T3 3511
valid_sources[0x73] 2378169 1 T1 42 T2 49 T3 3538
valid_sources[0x74] 1417118 1 T1 30 T2 42 T3 3767
valid_sources[0x75] 1483548 1 T1 35 T2 43 T3 3419
valid_sources[0x76] 1410711 1 T1 47 T2 57 T3 3449
valid_sources[0x77] 1456833 1 T1 34 T2 50 T3 3617
valid_sources[0x78] 1876245 1 T1 41 T2 38 T3 3567
valid_sources[0x79] 1403711 1 T1 32 T2 50 T3 3549
valid_sources[0x7a] 1417681 1 T1 47 T2 46 T3 3556
valid_sources[0x7b] 1428790 1 T1 37 T2 51 T3 3429
valid_sources[0x7c] 1407628 1 T1 31 T2 37 T3 3609
valid_sources[0x7d] 1492805 1 T1 29 T2 41 T3 3558
valid_sources[0x7e] 1453548 1 T1 51 T2 40 T3 3534
valid_sources[0x7f] 2653924 1 T1 54 T2 52 T3 3663
valid_sources[0x80] 1410082 1 T1 28 T2 42 T3 3508



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 86687320 1 T1 73328 T2 72991 T3 132599
values[0x0] all_enables biggest_size 60486093 1 T1 14879 T2 16002 T3 122833
values[0x1] all_enables biggest_size 51890174 1 T1 13060 T2 14267 T3 103702

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%