Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

254606905

1

T1

56033

T2

62393

T3

547515

full_word

199064371

1

T1

101267

T2

103260

T3

359134

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	453670986	1			T1	157300		T2	165653		T3	906649
auto[TlIntgErrCmd]	88	1			T102	4		T103	3		T104	11
auto[TlIntgErrData]	112	1			T102	3		T103	8		T104	4
auto[TlIntgErrBoth]	90	1			T102	3		T103	9		T104	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

239506094

1

T1

107245

T2

110903

T3

462755

auto[1]

214165182

1

T1

50055

T2

54750

T3

443894

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	152818464	1			T1	33917		T2	37912		T3	330156
auto[TlIntgErrNone]	partial	auto[1]	101788177	1			T1	22116		T2	24481		T3	217359
auto[TlIntgErrNone]	full_word	auto[0]	86687499	1			T1	73328		T2	72991		T3	132599
auto[TlIntgErrNone]	full_word	auto[1]	112376846	1			T1	27939		T2	30269		T3	226535
auto[TlIntgErrCmd]	partial	auto[0]	34	1			T102	2		T103	1		T104	6
auto[TlIntgErrCmd]	partial	auto[1]	46	1			T102	2		T103	2		T104	5
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T160	1		T161	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T159	1		T162	1		T160	1
auto[TlIntgErrData]	partial	auto[0]	57	1			T102	1		T103	4		T104	3
auto[TlIntgErrData]	partial	auto[1]	44	1			T102	2		T103	2		T104	1
auto[TlIntgErrData]	full_word	auto[0]	4	1			T103	2		T162	1		T163	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T156	2		T158	1		T162	1
auto[TlIntgErrBoth]	partial	auto[0]	30	1			T102	1		T103	4		T104	3
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T102	2		T103	4		T104	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T158	1		T164	1		T165	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T103	1		T166	1		T111	1