Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	3216	0	0
entropy_period_rd_A	2147483647	1548	0	0
intr_enable_rd_A	2147483647	2194	0	0
prefix_0_rd_A	2147483647	1774	0	0
prefix_10_rd_A	2147483647	1661	0	0
prefix_1_rd_A	2147483647	1468	0	0
prefix_2_rd_A	2147483647	1680	0	0
prefix_3_rd_A	2147483647	1564	0	0
prefix_4_rd_A	2147483647	1666	0	0
prefix_5_rd_A	2147483647	1679	0	0
prefix_6_rd_A	2147483647	1653	0	0
prefix_7_rd_A	2147483647	1668	0	0
prefix_8_rd_A	2147483647	1738	0	0
prefix_9_rd_A	2147483647	1544	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3216	0	0
T50	2126	2	0	0
T51	4525	51	0	0
T52	4451	188	0	0
T101	10926	176	0	0
T103	18515	2	0	0
T105	10786	252	0	0
T107	2815	158	0	0
T117	3649	4	0	0
T120	2194	5	0	0
T121	2473	20	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1548	0	0
T89	7351	52	0	0
T93	5853	34	0	0
T95	11876	61	0	0
T96	11611	25	0	0
T132	2743	5	0	0
T133	11085	47	0	0
T134	23810	107	0	0
T135	8992	20	0	0
T136	144557	233	0	0
T137	10414	29	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2194	0	0
T89	7351	39	0	0
T93	5853	52	0	0
T95	11876	82	0	0
T96	11611	55	0	0
T132	2743	15	0	0
T133	11085	60	0	0
T134	23810	114	0	0
T135	8992	27	0	0
T138	1739	4	0	0
T139	1760	32	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1774	0	0
T89	7351	15	0	0
T93	5853	16	0	0
T95	11876	43	0	0
T96	11611	17	0	0
T114	7070	2	0	0
T132	2743	15	0	0
T133	11085	81	0	0
T134	23810	93	0	0
T135	8992	10	0	0
T136	144557	446	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1661	0	0
T89	7351	19	0	0
T93	5853	22	0	0
T95	11876	61	0	0
T96	11611	20	0	0
T132	2743	2	0	0
T133	11085	32	0	0
T134	23810	121	0	0
T135	8992	9	0	0
T136	144557	401	0	0
T138	1739	2	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1468	0	0
T89	7351	23	0	0
T93	5853	12	0	0
T95	11876	41	0	0
T96	11611	10	0	0
T132	2743	1	0	0
T133	11085	58	0	0
T134	23810	93	0	0
T135	8992	15	0	0
T136	144557	430	0	0
T137	10414	31	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1680	0	0
T89	7351	25	0	0
T93	5853	20	0	0
T95	11876	54	0	0
T96	11611	11	0	0
T132	2743	10	0	0
T133	11085	6	0	0
T134	23810	118	0	0
T135	8992	15	0	0
T136	144557	468	0	0
T137	10414	65	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1564	0	0
T89	7351	21	0	0
T93	5853	27	0	0
T95	11876	56	0	0
T96	11611	22	0	0
T132	2743	12	0	0
T133	11085	44	0	0
T134	23810	121	0	0
T135	8992	14	0	0
T136	144557	402	0	0
T138	1739	4	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1666	0	0
T89	7351	19	0	0
T93	5853	17	0	0
T95	11876	59	0	0
T96	11611	28	0	0
T132	2743	10	0	0
T133	11085	76	0	0
T134	23810	137	0	0
T135	8992	14	0	0
T136	144557	406	0	0
T138	1739	8	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1679	0	0
T89	7351	30	0	0
T93	5853	24	0	0
T95	11876	51	0	0
T96	11611	27	0	0
T101	10926	3	0	0
T132	2743	7	0	0
T133	11085	29	0	0
T134	23810	119	0	0
T135	8992	14	0	0
T136	144557	470	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1653	0	0
T89	7351	34	0	0
T93	5853	26	0	0
T95	11876	35	0	0
T96	11611	26	0	0
T101	10926	9	0	0
T132	2743	6	0	0
T133	11085	46	0	0
T134	23810	111	0	0
T135	8992	15	0	0
T136	144557	537	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1668	0	0
T89	7351	25	0	0
T93	5853	29	0	0
T95	11876	49	0	0
T96	11611	31	0	0
T132	2743	4	0	0
T133	11085	38	0	0
T134	23810	99	0	0
T135	8992	11	0	0
T136	144557	437	0	0
T138	1739	7	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1738	0	0
T89	7351	17	0	0
T93	5853	36	0	0
T95	11876	52	0	0
T96	11611	22	0	0
T132	2743	1	0	0
T133	11085	6	0	0
T134	23810	190	0	0
T135	8992	12	0	0
T136	144557	491	0	0
T138	1739	1	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1544	0	0
T89	7351	32	0	0
T93	5853	20	0	0
T95	11876	48	0	0
T96	11611	15	0	0
T101	10926	4	0	0
T114	7070	5	0	0
T132	2743	11	0	0
T133	11085	80	0	0
T134	23810	114	0	0
T135	8992	8	0	0