Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	257515698	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

201587920

1

T1

93467

T2

1425

T3

2658

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	242424115	1			T1	99805		T2	1069		T3	2702
values[0x0]	104141518	1			T1	21423		T2	490		T3	637
values[0x1]	112537985	1			T1	22942		T2	490		T3	630

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	200817390	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

258286228

1

T1

104801

T2

1554

T3

2912

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1433084	1			T1	40		T2	5		T14	121
valid_sources[0x01]	2295450	1			T1	35		T2	10		T3	2
valid_sources[0x02]	1556231	1			T1	39		T3	4		T14	134
valid_sources[0x03]	1413222	1			T1	42		T2	6		T14	124
valid_sources[0x04]	2029566	1			T1	40		T2	9		T3	2
valid_sources[0x05]	1359556	1			T1	35		T2	10		T14	112
valid_sources[0x06]	1356942	1			T1	38		T2	7		T14	127
valid_sources[0x07]	2811395	1			T1	24		T2	9		T3	3
valid_sources[0x08]	1407531	1			T1	33		T2	13		T3	1
valid_sources[0x09]	1818991	1			T1	43		T2	15		T14	141
valid_sources[0x0a]	3028161	1			T1	40		T2	3		T14	125
valid_sources[0x0b]	1822386	1			T1	38		T2	14		T3	1
valid_sources[0x0c]	1539873	1			T1	39		T2	8		T14	130
valid_sources[0x0d]	3750475	1			T1	57		T2	7		T3	1
valid_sources[0x0e]	1371891	1			T1	36		T2	18		T3	3
valid_sources[0x0f]	1391838	1			T1	33		T2	10		T3	1
valid_sources[0x10]	1357862	1			T1	38		T2	10		T3	1
valid_sources[0x11]	1363675	1			T1	43		T2	16		T3	2
valid_sources[0x12]	2372195	1			T1	46		T2	11		T3	4
valid_sources[0x13]	1377780	1			T1	30		T2	8		T14	168
valid_sources[0x14]	1705870	1			T1	31		T2	8		T3	2
valid_sources[0x15]	1363196	1			T1	37		T2	6		T3	2
valid_sources[0x16]	1382973	1			T1	29		T2	13		T3	3
valid_sources[0x17]	1375748	1			T1	45		T2	20		T3	2
valid_sources[0x18]	1364715	1			T1	37		T2	14		T3	3
valid_sources[0x19]	4814673	1			T1	41		T2	11		T3	2
valid_sources[0x1a]	1452348	1			T1	33		T2	7		T3	1
valid_sources[0x1b]	1835420	1			T1	47		T2	7		T3	1
valid_sources[0x1c]	6160042	1			T1	40		T2	8		T3	1
valid_sources[0x1d]	1370674	1			T1	25		T2	9		T3	3
valid_sources[0x1e]	1356722	1			T1	36		T2	8		T3	1
valid_sources[0x1f]	1362932	1			T1	27		T2	7		T3	1
valid_sources[0x20]	1389634	1			T1	49		T2	8		T14	142
valid_sources[0x21]	1363661	1			T1	32		T2	4		T3	3
valid_sources[0x22]	1399929	1			T1	36		T2	8		T14	121
valid_sources[0x23]	1359547	1			T1	35		T2	5		T14	166
valid_sources[0x24]	2164078	1			T1	41		T2	6		T3	1
valid_sources[0x25]	1456477	1			T1	42		T2	7		T3	1
valid_sources[0x26]	1359118	1			T1	29		T2	7		T3	3
valid_sources[0x27]	1350773	1			T1	38		T2	9		T3	1
valid_sources[0x28]	1359018	1			T1	46		T2	3		T3	3
valid_sources[0x29]	1367350	1			T1	36		T2	8		T3	1
valid_sources[0x2a]	2029824	1			T1	37		T2	17		T3	1
valid_sources[0x2b]	2037839	1			T1	45		T2	6		T3	2
valid_sources[0x2c]	2359766	1			T1	38		T2	4		T3	4
valid_sources[0x2d]	1393961	1			T1	39		T2	13		T3	3
valid_sources[0x2e]	1351915	1			T1	34		T2	10		T3	1
valid_sources[0x2f]	3415807	1			T1	44		T2	10		T14	118
valid_sources[0x30]	1360915	1			T1	44		T2	11		T3	1
valid_sources[0x31]	1618570	1			T1	43		T2	2		T14	157
valid_sources[0x32]	1354630	1			T1	32		T2	8		T3	2
valid_sources[0x33]	1565035	1			T1	33		T2	8		T3	1
valid_sources[0x34]	1360473	1			T1	32		T2	10		T3	1
valid_sources[0x35]	1364555	1			T1	35		T2	7		T3	1
valid_sources[0x36]	3440159	1			T1	28		T2	10		T3	2
valid_sources[0x37]	1364968	1			T1	36		T2	8		T3	1
valid_sources[0x38]	1356513	1			T1	35		T2	8		T14	128
valid_sources[0x39]	1508287	1			T1	27		T2	3		T14	130
valid_sources[0x3a]	1362692	1			T1	36		T2	7		T3	1
valid_sources[0x3b]	1474709	1			T1	29		T2	7		T3	1
valid_sources[0x3c]	1360453	1			T1	35		T2	3		T14	165
valid_sources[0x3d]	1366025	1			T1	42		T2	7		T3	1
valid_sources[0x3e]	1366526	1			T1	28		T2	8		T3	2
valid_sources[0x3f]	1499580	1			T1	37		T2	11		T3	3
valid_sources[0x40]	1374098	1			T1	38		T2	9		T3	2
valid_sources[0x41]	1644819	1			T1	39		T2	9		T14	110
valid_sources[0x42]	1441428	1			T1	34		T2	2		T3	2
valid_sources[0x43]	1362194	1			T1	41		T2	6		T3	2
valid_sources[0x44]	1356840	1			T1	37		T2	10		T3	2
valid_sources[0x45]	1881442	1			T1	47		T2	17		T3	4
valid_sources[0x46]	3411708	1			T1	39		T2	12		T3	2
valid_sources[0x47]	2239080	1			T1	41		T2	6		T3	1
valid_sources[0x48]	4295721	1			T1	32		T2	7		T3	1
valid_sources[0x49]	1658542	1			T1	41		T2	10		T14	87
valid_sources[0x4a]	1360965	1			T1	35		T2	6		T3	2
valid_sources[0x4b]	2230789	1			T1	41		T2	9		T3	3
valid_sources[0x4c]	3384716	1			T1	26		T2	9		T3	3
valid_sources[0x4d]	3806124	1			T1	36		T2	12		T3	1
valid_sources[0x4e]	1357323	1			T1	31		T2	11		T3	3
valid_sources[0x4f]	1469600	1			T1	37		T2	9		T3	2
valid_sources[0x50]	2302503	1			T1	33		T2	4		T3	2
valid_sources[0x51]	1358446	1			T1	25		T2	4		T14	132
valid_sources[0x52]	6737675	1			T1	32		T2	6		T14	140
valid_sources[0x53]	3791343	1			T1	37		T2	7		T14	99
valid_sources[0x54]	2346252	1			T1	40		T2	18		T3	2
valid_sources[0x55]	1363468	1			T1	40		T2	10		T3	4
valid_sources[0x56]	1526193	1			T1	134709		T2	6		T3	1
valid_sources[0x57]	1362488	1			T1	41		T2	14		T3	3
valid_sources[0x58]	3373908	1			T1	41		T2	4		T3	1
valid_sources[0x59]	2249581	1			T1	34		T2	8		T3	4
valid_sources[0x5a]	3109505	1			T1	35		T2	3		T3	3
valid_sources[0x5b]	1385275	1			T1	37		T2	5		T14	116
valid_sources[0x5c]	1358717	1			T1	22		T2	13		T14	158
valid_sources[0x5d]	2884186	1			T1	31		T2	6		T3	2
valid_sources[0x5e]	1365298	1			T1	42		T2	8		T3	1
valid_sources[0x5f]	1365663	1			T1	36		T2	6		T3	3
valid_sources[0x60]	1361268	1			T1	37		T2	10		T3	2
valid_sources[0x61]	1362495	1			T1	37		T2	9		T3	1
valid_sources[0x62]	1372242	1			T1	30		T2	2		T14	169
valid_sources[0x63]	1349829	1			T1	40		T2	8		T3	1
valid_sources[0x64]	1360367	1			T1	34		T2	6		T3	2
valid_sources[0x65]	2140830	1			T1	42		T2	8		T3	3
valid_sources[0x66]	2347613	1			T1	38		T2	8		T3	3
valid_sources[0x67]	3265499	1			T1	33		T2	16		T3	1
valid_sources[0x68]	2393561	1			T1	49		T2	9		T3	1
valid_sources[0x69]	1358288	1			T1	32		T2	7		T14	133
valid_sources[0x6a]	1413021	1			T1	26		T2	8		T3	4
valid_sources[0x6b]	1358878	1			T1	35		T2	8		T3	1
valid_sources[0x6c]	3411329	1			T1	32		T2	8		T3	2
valid_sources[0x6d]	3729879	1			T1	35		T2	14		T3	1
valid_sources[0x6e]	1646601	1			T1	45		T2	12		T3	1
valid_sources[0x6f]	1364774	1			T1	29		T2	9		T3	3
valid_sources[0x70]	1361747	1			T1	35		T2	9		T3	1
valid_sources[0x71]	1359337	1			T1	43		T2	6		T3	2
valid_sources[0x72]	2420191	1			T1	38		T2	6		T3	1
valid_sources[0x73]	2217347	1			T1	44		T2	7		T3	3
valid_sources[0x74]	2034936	1			T1	33		T2	12		T3	3
valid_sources[0x75]	1407222	1			T1	36		T2	9		T3	2
valid_sources[0x76]	1359696	1			T1	39		T2	6		T3	2
valid_sources[0x77]	1364357	1			T1	44		T2	4		T3	4
valid_sources[0x78]	1352375	1			T1	34		T2	7		T3	3
valid_sources[0x79]	1425023	1			T1	52		T2	5		T3	3
valid_sources[0x7a]	1360095	1			T1	42		T2	8		T3	1
valid_sources[0x7b]	1360689	1			T1	33		T2	5		T3	2
valid_sources[0x7c]	1356872	1			T1	42		T2	8		T14	145
valid_sources[0x7d]	1364592	1			T1	31		T2	13		T14	134
valid_sources[0x7e]	1357041	1			T1	43		T2	4		T3	5
valid_sources[0x7f]	1362918	1			T1	45		T2	9		T14	140
valid_sources[0x80]	1439036	1			T1	43		T2	7		T14	134

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

87944226

1

T1

69311

T2

696

T3

1828

values[0x0]

all_enables

biggest_size

61169812

1

T1

13011

T2

373

T3

452

values[0x1]

all_enables

biggest_size

52473882

1

T1

11145

T2

356

T3

378