SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[kmac_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 313559334 | 1 | T1 | 66126 | T2 | 1269 | T3 | 1895 | ||||
auto[1] | 146303733 | 1 | T1 | 78044 | T2 | 780 | T3 | 2074 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 459862859 | 1 | T1 | 144170 | T2 | 2049 | T3 | 3969 | ||||
values[1] | 21 | 1 | T119 | 1 | T120 | 1 | T121 | 1 | ||||
values[2] | 6 | 1 | T176 | 1 | T148 | 1 | T177 | 2 | ||||
values[3] | 107 | 1 | T119 | 3 | T120 | 8 | T121 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 459862867 | 1 | T1 | 144170 | T2 | 2049 | T3 | 3969 | ||||
values[1] | 18 | 1 | T119 | 2 | T120 | 1 | T121 | 1 | ||||
values[2] | 3 | 1 | T178 | 1 | T177 | 1 | T179 | 1 | ||||
values[3] | 100 | 1 | T119 | 3 | T120 | 11 | T121 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 459862767 | 1 | T1 | 144170 | T2 | 2049 | T3 | 3969 | ||||
auto[TlIntgErrCmd] | 100 | 1 | T119 | 4 | T120 | 3 | T121 | 3 | ||||
auto[TlIntgErrData] | 92 | 1 | T119 | 4 | T120 | 6 | T121 | 2 | ||||
auto[TlIntgErrBoth] | 108 | 1 | T119 | 2 | T120 | 11 | T121 | 5 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |