Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

258229885

1

T1

50703

T2

624

T3

1311

full_word

201633182

1

T1

93467

T2

1425

T3

2658

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	459862767	1			T1	144170		T2	2049		T3	3969
auto[TlIntgErrCmd]	100	1			T119	4		T120	3		T121	3
auto[TlIntgErrData]	92	1			T119	4		T120	6		T121	2
auto[TlIntgErrBoth]	108	1			T119	2		T120	11		T121	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

242563689

1

T1

99805

T2

1069

T3

2702

auto[1]

217299378

1

T1

44365

T2

980

T3

1267

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	154607875	1			T1	30494		T2	373		T3	874
auto[TlIntgErrNone]	partial	auto[1]	103621738	1			T1	20209		T2	251		T3	437
auto[TlIntgErrNone]	full_word	auto[0]	87955681	1			T1	69311		T2	696		T3	1828
auto[TlIntgErrNone]	full_word	auto[1]	113677473	1			T1	24156		T2	729		T3	830
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T119	1		T120	1		T121	3
auto[TlIntgErrCmd]	partial	auto[1]	47	1			T119	2		T120	1		T180	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T120	1		T181	2		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T119	1		T180	1		T176	1
auto[TlIntgErrData]	partial	auto[0]	36	1			T119	2		T120	2		T121	1
auto[TlIntgErrData]	partial	auto[1]	47	1			T119	2		T120	3		T121	1
auto[TlIntgErrData]	full_word	auto[0]	6	1			T120	1		T176	1		T178	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T182	1		T179	1		T183	1
auto[TlIntgErrBoth]	partial	auto[0]	44	1			T120	6		T121	4		T184	3
auto[TlIntgErrBoth]	partial	auto[1]	56	1			T119	2		T120	5		T121	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T176	1		T181	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T178	1		T148	1		T185	2