Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	167171	0	0
entropy_period_rd_A	2147483647	1051	0	0
intr_enable_rd_A	2147483647	1518	0	0
prefix_0_rd_A	2147483647	1072	0	0
prefix_10_rd_A	2147483647	1002	0	0
prefix_1_rd_A	2147483647	925	0	0
prefix_2_rd_A	2147483647	987	0	0
prefix_3_rd_A	2147483647	912	0	0
prefix_4_rd_A	2147483647	916	0	0
prefix_5_rd_A	2147483647	907	0	0
prefix_6_rd_A	2147483647	988	0	0
prefix_7_rd_A	2147483647	939	0	0
prefix_8_rd_A	2147483647	892	0	0
prefix_9_rd_A	2147483647	908	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	167171	0	0
T40	245655	36337	0	0
T50	0	104099	0	0
T51	0	23786	0	0
T79	186885	0	0	0
T80	339387	0	0	0
T125	0	109	0	0
T126	0	1	0	0
T127	0	3	0	0
T128	0	179	0	0
T129	0	6	0	0
T130	0	9	0	0
T131	0	1	0	0
T132	23037	0	0	0
T133	1082	0	0	0
T134	429643	0	0	0
T135	148195	0	0	0
T136	378037	0	0	0
T137	256608	0	0	0
T138	324424	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1051	0	0
T109	6734	47	0	0
T110	12296	99	0	0
T119	10692	45	0	0
T126	4300	4	0	0
T145	12397	44	0	0
T146	7757	19	0	0
T147	5143	18	0	0
T148	21104	47	0	0
T149	2557	4	0	0
T150	6573	46	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1518	0	0
T110	12296	38	0	0
T119	10692	32	0	0
T123	1061	27	0	0
T145	12397	41	0	0
T146	7757	35	0	0
T147	5143	35	0	0
T148	21104	99	0	0
T151	1535	12	0	0
T152	1271	21	0	0
T153	7352	15	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1072	0	0
T110	12296	44	0	0
T119	10692	32	0	0
T126	4300	13	0	0
T145	12397	49	0	0
T146	7757	25	0	0
T147	5143	15	0	0
T148	21104	59	0	0
T149	2557	4	0	0
T153	7352	14	0	0
T154	2041	8	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1002	0	0
T110	12296	36	0	0
T119	10692	29	0	0
T126	4300	3	0	0
T145	12397	64	0	0
T146	7757	13	0	0
T147	5143	22	0	0
T148	21104	41	0	0
T149	2557	13	0	0
T153	7352	17	0	0
T154	2041	2	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	925	0	0
T110	12296	54	0	0
T119	10692	3	0	0
T145	12397	59	0	0
T146	7757	18	0	0
T147	5143	4	0	0
T148	21104	58	0	0
T149	2557	8	0	0
T153	7352	10	0	0
T154	2041	3	0	0
T155	11580	4	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	987	0	0
T110	12296	42	0	0
T119	10692	30	0	0
T145	12397	72	0	0
T146	7757	24	0	0
T147	5143	3	0	0
T148	21104	72	0	0
T149	2557	10	0	0
T150	6573	27	0	0
T153	7352	9	0	0
T154	2041	10	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	912	0	0
T110	12296	67	0	0
T119	10692	40	0	0
T125	6031	7	0	0
T126	4300	1	0	0
T145	12397	48	0	0
T146	7757	7	0	0
T147	5143	20	0	0
T148	21104	48	0	0
T149	2557	4	0	0
T153	7352	5	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	916	0	0
T110	12296	53	0	0
T119	10692	20	0	0
T126	4300	11	0	0
T145	12397	4	0	0
T146	7757	31	0	0
T147	5143	14	0	0
T148	21104	33	0	0
T149	2557	10	0	0
T153	7352	10	0	0
T155	11580	4	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	907	0	0
T110	12296	50	0	0
T119	10692	25	0	0
T145	12397	10	0	0
T146	7757	25	0	0
T147	5143	11	0	0
T148	21104	49	0	0
T149	2557	7	0	0
T150	6573	19	0	0
T153	7352	9	0	0
T154	2041	1	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	988	0	0
T110	12296	57	0	0
T119	10692	15	0	0
T145	12397	82	0	0
T146	7757	15	0	0
T147	5143	11	0	0
T148	21104	54	0	0
T149	2557	3	0	0
T150	6573	30	0	0
T153	7352	9	0	0
T154	2041	3	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	939	0	0
T110	12296	41	0	0
T119	10692	29	0	0
T125	6031	7	0	0
T126	4300	4	0	0
T145	12397	59	0	0
T146	7757	13	0	0
T147	5143	17	0	0
T148	21104	23	0	0
T149	2557	10	0	0
T153	7352	6	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	892	0	0
T110	12296	65	0	0
T119	10692	27	0	0
T126	4300	5	0	0
T145	12397	34	0	0
T146	7757	20	0	0
T147	5143	7	0	0
T148	21104	57	0	0
T149	2557	8	0	0
T153	7352	5	0	0
T154	2041	9	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	908	0	0
T110	12296	53	0	0
T119	10692	35	0	0
T126	4300	6	0	0
T145	12397	27	0	0
T146	7757	23	0	0
T147	5143	20	0	0
T148	21104	52	0	0
T149	2557	17	0	0
T153	7352	5	0	0
T155	11580	5	0	0