Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	257091535	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

201053673

1

T1

359361

T2

40415

T3

663

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	241837931	1			T1	463269		T2	43157		T3	378
values[0x0]	103974424	1			T1	214003		T2	10329		T3	312
values[0x1]	112332853	1			T1	230410		T2	10977		T3	377

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	200500703	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

257644505

1

T1

478796

T2

45852

T3

773

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1359680	1			T1	3707		T2	24		T3	2
valid_sources[0x01]	1348095	1			T1	3428		T2	19		T3	5
valid_sources[0x02]	1472526	1			T1	3569		T2	19		T3	9
valid_sources[0x03]	3408014	1			T1	3443		T2	14		T3	5
valid_sources[0x04]	2815948	1			T1	3555		T2	22		T3	2
valid_sources[0x05]	2262276	1			T1	3543		T2	26		T3	1
valid_sources[0x06]	1364588	1			T1	3606		T2	22		T3	3
valid_sources[0x07]	1405299	1			T1	3304		T2	27		T3	2
valid_sources[0x08]	1350853	1			T1	3671		T2	27		T3	6
valid_sources[0x09]	1350722	1			T1	3667		T2	19		T3	5
valid_sources[0x0a]	4722616	1			T1	3756		T2	22		T3	3
valid_sources[0x0b]	1355713	1			T1	3317		T2	21		T3	5
valid_sources[0x0c]	1350125	1			T1	3243		T2	27		T3	4
valid_sources[0x0d]	1354280	1			T1	3515		T2	23		T3	5
valid_sources[0x0e]	1364531	1			T1	3796		T2	16		T3	1
valid_sources[0x0f]	1413168	1			T1	3501		T2	18		T3	4
valid_sources[0x10]	1349580	1			T1	3293		T2	23		T3	5
valid_sources[0x11]	1357437	1			T1	3783		T2	26		T3	5
valid_sources[0x12]	2256789	1			T1	3795		T2	26		T3	6
valid_sources[0x13]	2891151	1			T1	4119		T2	21		T3	4
valid_sources[0x14]	1366300	1			T1	3559		T2	27		T3	7
valid_sources[0x15]	1460216	1			T1	3613		T2	15		T3	2
valid_sources[0x16]	1370525	1			T1	3535		T2	17		T3	2
valid_sources[0x17]	1363112	1			T1	3533		T2	24		T3	3
valid_sources[0x18]	1355026	1			T1	3512		T2	28		T3	5
valid_sources[0x19]	1817024	1			T1	3527		T2	30		T3	6
valid_sources[0x1a]	1528103	1			T1	3660		T2	20		T3	4
valid_sources[0x1b]	2704750	1			T1	3583		T2	20		T3	4
valid_sources[0x1c]	3398689	1			T1	3650		T2	18		T3	2
valid_sources[0x1d]	1350046	1			T1	3842		T2	24		T3	8
valid_sources[0x1e]	1354255	1			T1	3386		T2	16		T3	4
valid_sources[0x1f]	1352857	1			T1	3363		T2	23		T3	4
valid_sources[0x20]	1349081	1			T1	3455		T2	16		T3	9
valid_sources[0x21]	1519156	1			T1	3238		T2	24		T3	1
valid_sources[0x22]	1362126	1			T1	3820		T2	23		T3	8
valid_sources[0x23]	1398433	1			T1	3613		T2	21		T3	4
valid_sources[0x24]	3745063	1			T1	3862		T2	17		T3	5
valid_sources[0x25]	1357406	1			T1	3331		T2	14		T3	4
valid_sources[0x26]	1474688	1			T1	3902		T2	20		T3	6
valid_sources[0x27]	1351062	1			T1	3196		T2	18		T3	6
valid_sources[0x28]	1520667	1			T1	3674		T2	25		T3	4
valid_sources[0x29]	1351082	1			T1	3727		T2	27		T3	2
valid_sources[0x2a]	1360382	1			T1	3362		T2	19		T3	3
valid_sources[0x2b]	2271205	1			T1	3694		T2	17		T3	4
valid_sources[0x2c]	1420507	1			T1	3238		T2	20		T3	3
valid_sources[0x2d]	1414208	1			T1	3477		T2	16		T3	5
valid_sources[0x2e]	3750280	1			T1	3146		T2	21		T3	4
valid_sources[0x2f]	1356110	1			T1	3445		T2	20		T3	2
valid_sources[0x30]	2228485	1			T1	3728		T2	18		T3	3
valid_sources[0x31]	3597959	1			T1	3439		T2	11		T3	5
valid_sources[0x32]	1470941	1			T1	3586		T2	18		T3	8
valid_sources[0x33]	1351608	1			T1	3438		T2	21		T3	2
valid_sources[0x34]	1359718	1			T1	3461		T2	23		T3	5
valid_sources[0x35]	1554598	1			T1	4047		T2	19		T3	4
valid_sources[0x36]	1347956	1			T1	3761		T2	21		T3	8
valid_sources[0x37]	3524636	1			T1	3505		T2	30		T3	4
valid_sources[0x38]	1358426	1			T1	3299		T2	17		T3	8
valid_sources[0x39]	3827317	1			T1	3326		T2	18		T3	4
valid_sources[0x3a]	1351755	1			T1	3940		T2	18		T3	10
valid_sources[0x3b]	1362090	1			T1	3794		T2	17		T3	2
valid_sources[0x3c]	1560282	1			T1	3647		T2	27		T3	3
valid_sources[0x3d]	1415764	1			T1	3500		T2	18		T3	3
valid_sources[0x3e]	1354014	1			T1	3493		T2	14		T3	3
valid_sources[0x3f]	1819162	1			T1	3495		T2	20		T3	3
valid_sources[0x40]	1355037	1			T1	3692		T2	24		T3	2
valid_sources[0x41]	1357891	1			T1	3401		T2	24		T3	6
valid_sources[0x42]	1358006	1			T1	3829		T2	16		T3	5
valid_sources[0x43]	1347968	1			T1	3428		T2	16		T3	7
valid_sources[0x44]	2270158	1			T1	3335		T2	24		T3	3
valid_sources[0x45]	4748202	1			T1	3774		T2	22		T3	3
valid_sources[0x46]	1385765	1			T1	3682		T2	12		T3	2
valid_sources[0x47]	1350121	1			T1	3702		T2	17		T3	1
valid_sources[0x48]	1355521	1			T1	3399		T2	24		T3	7
valid_sources[0x49]	2020990	1			T1	3421		T2	16		T3	1
valid_sources[0x4a]	1460002	1			T1	3671		T2	21		T3	3
valid_sources[0x4b]	1441702	1			T1	3922		T2	29		T3	1
valid_sources[0x4c]	1358825	1			T1	3644		T2	22		T3	6
valid_sources[0x4d]	1355767	1			T1	3679		T2	25		T3	3
valid_sources[0x4e]	1356940	1			T1	3329		T2	21		T3	3
valid_sources[0x4f]	1358336	1			T1	3754		T2	17		T13	5
valid_sources[0x50]	1827218	1			T1	3258		T2	11		T3	3
valid_sources[0x51]	1355443	1			T1	3357		T2	18		T3	4
valid_sources[0x52]	1355415	1			T1	3889		T2	32		T3	1
valid_sources[0x53]	3420971	1			T1	3451		T2	26		T3	4
valid_sources[0x54]	1396994	1			T1	3603		T2	28		T3	1
valid_sources[0x55]	1822802	1			T1	3390		T2	23		T3	1
valid_sources[0x56]	5774997	1			T1	3277		T2	21		T3	4
valid_sources[0x57]	3417645	1			T1	3506		T2	20		T3	7
valid_sources[0x58]	1348893	1			T1	3570		T2	23		T3	5
valid_sources[0x59]	1384068	1			T1	3465		T2	27		T3	1
valid_sources[0x5a]	2271136	1			T1	3495		T2	20		T3	3
valid_sources[0x5b]	1354851	1			T1	3864		T2	22		T3	8
valid_sources[0x5c]	1355161	1			T1	3601		T2	25		T3	6
valid_sources[0x5d]	2025265	1			T1	3951		T2	20		T3	5
valid_sources[0x5e]	1358424	1			T1	3426		T2	25		T3	3
valid_sources[0x5f]	1354567	1			T1	3087		T2	28		T3	3
valid_sources[0x60]	1357323	1			T1	3899		T2	21		T3	6
valid_sources[0x61]	1370578	1			T1	3483		T2	25		T3	3
valid_sources[0x62]	1517878	1			T1	3745		T2	26		T13	11
valid_sources[0x63]	1357780	1			T1	3641		T2	16		T3	3
valid_sources[0x64]	1357693	1			T1	3522		T2	25		T3	5
valid_sources[0x65]	2228046	1			T1	3668		T2	25		T3	7
valid_sources[0x66]	1433661	1			T1	3642		T2	23		T3	8
valid_sources[0x67]	1353971	1			T1	3622		T2	27		T3	3
valid_sources[0x68]	1353259	1			T1	3453		T2	14		T3	3
valid_sources[0x69]	1354188	1			T1	4003		T2	22		T3	2
valid_sources[0x6a]	1355056	1			T1	3652		T2	19		T3	6
valid_sources[0x6b]	1352278	1			T1	3691		T2	22		T3	1
valid_sources[0x6c]	1355557	1			T1	3891		T2	12		T3	5
valid_sources[0x6d]	3757786	1			T1	3512		T2	30		T3	4
valid_sources[0x6e]	1360572	1			T1	3736		T2	26		T3	5
valid_sources[0x6f]	1351783	1			T1	3337		T2	21		T3	7
valid_sources[0x70]	1422555	1			T1	3468		T2	32		T3	11
valid_sources[0x71]	2225163	1			T1	3469		T2	25		T3	6
valid_sources[0x72]	1355145	1			T1	3448		T2	19		T3	2
valid_sources[0x73]	1349789	1			T1	3842		T2	9		T3	5
valid_sources[0x74]	1362889	1			T1	2923		T2	13		T3	2
valid_sources[0x75]	1360991	1			T1	3445		T2	14		T3	5
valid_sources[0x76]	1353188	1			T1	3759		T2	26		T3	4
valid_sources[0x77]	1354451	1			T1	3828		T2	23		T3	2
valid_sources[0x78]	1540096	1			T1	3444		T2	17		T3	2
valid_sources[0x79]	1354231	1			T1	3005		T2	23		T3	6
valid_sources[0x7a]	3757068	1			T1	3232		T2	24		T3	8
valid_sources[0x7b]	1478481	1			T1	3813		T2	23		T3	1
valid_sources[0x7c]	3781152	1			T1	3614		T2	24		T3	3
valid_sources[0x7d]	1359531	1			T1	3461		T2	30		T3	5
valid_sources[0x7e]	1357181	1			T1	3590		T2	20		T3	3
valid_sources[0x7f]	2272882	1			T1	3324		T2	16		T3	6
valid_sources[0x80]	2232162	1			T1	3308		T2	19		T3	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

87524546

1

T1

132631

T2

28666

T3

25

values[0x0]

all_enables

biggest_size

61102064

1

T1

122684

T2

6317

T3

286

values[0x1]

all_enables

biggest_size

52427063

1

T1

104046

T2

5432

T3

352