Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

257105462

1

T1

548321

T2

24048

T3

404

full_word

201054501

1

T1

359361

T2

40415

T3

663

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	458159673	1			T1	907682		T2	64463		T3	1067
auto[TlIntgErrCmd]	95	1			T51	3		T52	3		T108	4
auto[TlIntgErrData]	98	1			T51	2		T52	5		T108	3
auto[TlIntgErrBoth]	97	1			T51	5		T52	2		T108	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

241840427

1

T1

463269

T2

43157

T3

378

auto[1]

216319536

1

T1

444413

T2

21306

T3

689

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrCmd]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	154315543	1			T1	330638		T2	14491		T3	353
auto[TlIntgErrNone]	partial	auto[1]	102789649	1			T1	217683		T2	9557		T3	51
auto[TlIntgErrNone]	full_word	auto[0]	87524744	1			T1	132631		T2	28666		T3	25
auto[TlIntgErrNone]	full_word	auto[1]	113529737	1			T1	226730		T2	11749		T3	638
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T51	2		T52	3		T108	2
auto[TlIntgErrCmd]	partial	auto[1]	48	1			T51	1		T108	2		T109	3
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T132	2		T169	1		T170	1
auto[TlIntgErrData]	partial	auto[0]	46	1			T51	2		T52	2		T130	5
auto[TlIntgErrData]	partial	auto[1]	45	1			T52	2		T108	3		T109	1
auto[TlIntgErrData]	full_word	auto[0]	1	1			T131	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	6	1			T52	1		T171	2		T170	1
auto[TlIntgErrBoth]	partial	auto[0]	45	1			T51	2		T52	1		T108	2
auto[TlIntgErrBoth]	partial	auto[1]	43	1			T51	3		T52	1		T108	1
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T130	1		T171	1		T125	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T171	1		T172	1		T173	1