Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_arbiter_fixed
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.05 87.50 92.68 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_app_intf.u_appid_arb 95.05 87.50 92.68 100.00 100.00



Module Instance : tb.dut.u_app_intf.u_appid_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.05 87.50 92.68 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.05 87.50 92.68 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
80.04 90.99 84.93 37.78 86.52 100.00 u_app_intf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_arbiter_fixed
Line No.TotalCoveredPercent
TOTAL322887.50
CONT_ASSIGN8511100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN87100.00
CONT_ASSIGN87100.00
CONT_ASSIGN87100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9711100.00
ALWAYS10566100.00
ALWAYS10566100.00
ALWAYS10566100.00
CONT_ASSIGN124100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12911100.00
CONT_ASSIGN13211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
85 3 3
87 0 3
89 3 3
97 1 1
105 1 1
107 1 1
109 1 1
110 1 1
112 1 1
113 1 1
105 1 1
107 1 1
109 1 1
110 1 1
112 1 1
113 1 1
105 1 1
107 1 1
109 1 1
110 1 1
112 1 1
113 1 1
124 0 1
128 1 1
129 1 1
132 1 1


Cond Coverage for Module : prim_arbiter_fixed
TotalCoveredPercent
Conditions413892.68
Logical413892.68
Non-Logical00
Event00

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT2,T3,T4
01CoveredT2,T4,T17
10CoveredT2,T3,T4

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT2,T3,T4
01CoveredT2,T4,T17
10CoveredT2,T3,T4

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT2,T4,T17
01Unreachable
10CoveredT2,T4,T17

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1-StatusTests
0CoveredT2,T4,T17
1CoveredT2,T4,T17

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1-StatusTests
0CoveredT2,T4,T17
1CoveredT2,T4,T17

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT2,T4,T17
11CoveredT2,T3,T4

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT2,T17,T34
11CoveredT2,T3,T4

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT2,T4,T17
10Not Covered
11CoveredT2,T4,T17

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT2,T3,T4
11CoveredT2,T4,T17

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT2,T3,T4
11CoveredT2,T17,T34

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT2,T4,T17
10CoveredT2,T4,T17
11Not Covered

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---
-1--2-StatusTests
01Not Covered
10CoveredT2,T3,T4
11CoveredT2,T3,T4

Branch Coverage for Module : prim_arbiter_fixed
Line No.TotalCoveredPercent
Branches 12 12 100.00
TERNARY 109 2 2 100.00
TERNARY 110 2 2 100.00
TERNARY 109 2 2 100.00
TERNARY 110 2 2 100.00
TERNARY 109 2 2 100.00
TERNARY 110 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T2,T3,T4
0 Covered T2,T3,T4


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T2,T3,T4
0 Covered T2,T3,T4


LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T2,T3,T4
0 Covered T2,T3,T4


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T2,T3,T4
0 Covered T2,T3,T4


LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T2,T4,T17
0 Covered T2,T4,T17


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T2,T4,T17
0 Covered T2,T4,T17


Assert Coverage for Module : prim_arbiter_fixed
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 13 13 100.00 13 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 13 13 100.00 13 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckHotOne_A 2147483647 2147483647 0 0
CheckNGreaterZero_A 1021 1021 0 0
GntImpliesReady_A 2147483647 7100 0 0
GntImpliesValid_A 2147483647 7100 0 0
GrantKnown_A 2147483647 2147483647 0 0
IdxKnown_A 2147483647 2147483647 0 0
IndexIsCorrect_A 2147483647 7100 0 0
NoReadyValidNoGrant_A 2147483647 2147483647 0 0
Priority_A 2147483647 2255195 0 0
ReadyAndValidImplyGrant_A 2147483647 7100 0 0
ReqAndReadyImplyGrant_A 2147483647 7100 0 0
ReqImpliesValid_A 2147483647 2255195 0 0
ValidKnown_A 2147483647 2147483647 0 0


CheckHotOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 185459 185453 0 0
T2 621031 620953 0 0
T3 103789 103736 0 0
T4 39851 39718 0 0
T13 16700 16634 0 0
T14 176551 176544 0 0
T15 145427 145419 0 0
T16 189534 189445 0 0
T17 126550 126492 0 0
T18 16072 16002 0 0

CheckNGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1021 1021 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

GntImpliesReady_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 7100 0 0
T2 621031 34 0 0
T3 103789 13 0 0
T4 39851 5 0 0
T13 16700 0 0 0
T14 176551 0 0 0
T15 145427 0 0 0
T16 189534 0 0 0
T17 126550 61 0 0
T18 16072 0 0 0
T19 119747 13 0 0
T21 0 13 0 0
T22 0 40 0 0
T24 0 3 0 0
T34 0 4 0 0
T43 0 1 0 0

GntImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 7100 0 0
T2 621031 34 0 0
T3 103789 13 0 0
T4 39851 5 0 0
T13 16700 0 0 0
T14 176551 0 0 0
T15 145427 0 0 0
T16 189534 0 0 0
T17 126550 61 0 0
T18 16072 0 0 0
T19 119747 13 0 0
T21 0 13 0 0
T22 0 40 0 0
T24 0 3 0 0
T34 0 4 0 0
T43 0 1 0 0

GrantKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 185459 185453 0 0
T2 621031 620953 0 0
T3 103789 103736 0 0
T4 39851 39718 0 0
T13 16700 16634 0 0
T14 176551 176544 0 0
T15 145427 145419 0 0
T16 189534 189445 0 0
T17 126550 126492 0 0
T18 16072 16002 0 0

IdxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 185459 185453 0 0
T2 621031 620953 0 0
T3 103789 103736 0 0
T4 39851 39718 0 0
T13 16700 16634 0 0
T14 176551 176544 0 0
T15 145427 145419 0 0
T16 189534 189445 0 0
T17 126550 126492 0 0
T18 16072 16002 0 0

IndexIsCorrect_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 7100 0 0
T2 621031 34 0 0
T3 103789 13 0 0
T4 39851 5 0 0
T13 16700 0 0 0
T14 176551 0 0 0
T15 145427 0 0 0
T16 189534 0 0 0
T17 126550 61 0 0
T18 16072 0 0 0
T19 119747 13 0 0
T21 0 13 0 0
T22 0 40 0 0
T24 0 3 0 0
T34 0 4 0 0
T43 0 1 0 0

NoReadyValidNoGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 185459 185453 0 0
T2 621031 614764 0 0
T3 103789 103001 0 0
T4 39851 37879 0 0
T13 16700 16634 0 0
T14 176551 176544 0 0
T15 145427 145419 0 0
T16 189534 189445 0 0
T17 126550 125701 0 0
T18 16072 16002 0 0

Priority_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2255195 0 0
T2 621031 6189 0 0
T3 103789 735 0 0
T4 39851 1839 0 0
T5 0 776 0 0
T13 16700 0 0 0
T14 176551 0 0 0
T15 145427 0 0 0
T16 189534 0 0 0
T17 126550 7905 0 0
T18 16072 0 0 0
T19 119747 748 0 0
T21 0 769 0 0
T24 0 272 0 0
T34 0 987 0 0
T43 0 86 0 0

ReadyAndValidImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 7100 0 0
T2 621031 34 0 0
T3 103789 13 0 0
T4 39851 5 0 0
T13 16700 0 0 0
T14 176551 0 0 0
T15 145427 0 0 0
T16 189534 0 0 0
T17 126550 61 0 0
T18 16072 0 0 0
T19 119747 13 0 0
T21 0 13 0 0
T22 0 40 0 0
T24 0 3 0 0
T34 0 4 0 0
T43 0 1 0 0

ReqAndReadyImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 7100 0 0
T2 621031 34 0 0
T3 103789 13 0 0
T4 39851 5 0 0
T13 16700 0 0 0
T14 176551 0 0 0
T15 145427 0 0 0
T16 189534 0 0 0
T17 126550 61 0 0
T18 16072 0 0 0
T19 119747 13 0 0
T21 0 13 0 0
T22 0 40 0 0
T24 0 3 0 0
T34 0 4 0 0
T43 0 1 0 0

ReqImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2255195 0 0
T2 621031 6189 0 0
T3 103789 735 0 0
T4 39851 1839 0 0
T5 0 776 0 0
T13 16700 0 0 0
T14 176551 0 0 0
T15 145427 0 0 0
T16 189534 0 0 0
T17 126550 7905 0 0
T18 16072 0 0 0
T19 119747 748 0 0
T21 0 769 0 0
T24 0 272 0 0
T34 0 987 0 0
T43 0 86 0 0

ValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 185459 185453 0 0
T2 621031 620953 0 0
T3 103789 103736 0 0
T4 39851 39718 0 0
T13 16700 16634 0 0
T14 176551 176544 0 0
T15 145427 145419 0 0
T16 189534 189445 0 0
T17 126550 126492 0 0
T18 16072 16002 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%