Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	3666	0	0
entropy_period_rd_A	2147483647	1183	0	0
intr_enable_rd_A	2147483647	1787	0	0
prefix_0_rd_A	2147483647	1144	0	0
prefix_10_rd_A	2147483647	1040	0	0
prefix_1_rd_A	2147483647	1178	0	0
prefix_2_rd_A	2147483647	1060	0	0
prefix_3_rd_A	2147483647	1032	0	0
prefix_4_rd_A	2147483647	1164	0	0
prefix_5_rd_A	2147483647	919	0	0
prefix_6_rd_A	2147483647	1014	0	0
prefix_7_rd_A	2147483647	1042	0	0
prefix_8_rd_A	2147483647	972	0	0
prefix_9_rd_A	2147483647	1083	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3666	0	0
T50	2191	1	0	0
T51	16268	4	0	0
T52	5732	1	0	0
T105	3945	3	0	0
T106	3496	93	0	0
T107	9279	190	0	0
T108	9711	2	0	0
T109	9396	1	0	0
T129	3624	5	0	0
T131	9392	1	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1183	0	0
T51	16268	14	0	0
T94	4962	25	0	0
T95	2176	9	0	0
T105	3945	9	0	0
T126	24983	78	0	0
T130	14548	56	0	0
T142	5543	8	0	0
T143	12449	79	0	0
T144	3122	1	0	0
T145	10438	57	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1787	0	0
T51	16268	37	0	0
T94	4962	18	0	0
T105	3945	3	0	0
T120	1165	17	0	0
T121	1367	5	0	0
T130	14548	51	0	0
T142	5543	3	0	0
T143	12449	108	0	0
T146	1217	5	0	0
T147	1175	10	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1144	0	0
T51	16268	32	0	0
T94	4962	26	0	0
T95	2176	5	0	0
T105	3945	1	0	0
T126	24983	52	0	0
T130	14548	44	0	0
T142	5543	12	0	0
T143	12449	41	0	0
T145	10438	57	0	0
T148	2636	4	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1040	0	0
T51	16268	15	0	0
T95	2176	3	0	0
T105	3945	7	0	0
T126	24983	25	0	0
T130	14548	43	0	0
T142	5543	28	0	0
T143	12449	41	0	0
T145	10438	47	0	0
T148	2636	4	0	0
T149	3057	9	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1178	0	0
T51	16268	25	0	0
T94	4962	34	0	0
T95	2176	7	0	0
T105	3945	6	0	0
T126	24983	38	0	0
T130	14548	48	0	0
T142	5543	56	0	0
T143	12449	54	0	0
T144	3122	2	0	0
T145	10438	51	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1060	0	0
T51	16268	14	0	0
T94	4962	11	0	0
T95	2176	1	0	0
T105	3945	9	0	0
T126	24983	39	0	0
T130	14548	50	0	0
T142	5543	7	0	0
T143	12449	59	0	0
T144	3122	18	0	0
T145	10438	33	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1032	0	0
T51	16268	18	0	0
T94	4962	16	0	0
T126	24983	51	0	0
T130	14548	52	0	0
T142	5543	27	0	0
T143	12449	47	0	0
T144	3122	8	0	0
T145	10438	20	0	0
T148	2636	3	0	0
T149	3057	5	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1164	0	0
T51	16268	21	0	0
T94	4962	20	0	0
T95	2176	4	0	0
T122	12514	9	0	0
T126	24983	57	0	0
T130	14548	28	0	0
T142	5543	25	0	0
T143	12449	53	0	0
T144	3122	19	0	0
T145	10438	24	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	919	0	0
T51	16268	25	0	0
T94	4962	5	0	0
T95	2176	5	0	0
T105	3945	16	0	0
T126	24983	37	0	0
T130	14548	37	0	0
T143	12449	50	0	0
T144	3122	9	0	0
T145	10438	10	0	0
T148	2636	2	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1014	0	0
T51	16268	22	0	0
T95	2176	3	0	0
T105	3945	11	0	0
T126	24983	49	0	0
T130	14548	36	0	0
T142	5543	19	0	0
T143	12449	52	0	0
T144	3122	2	0	0
T145	10438	42	0	0
T148	2636	7	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1042	0	0
T51	16268	22	0	0
T94	4962	10	0	0
T95	2176	4	0	0
T105	3945	8	0	0
T126	24983	53	0	0
T130	14548	37	0	0
T142	5543	23	0	0
T143	12449	63	0	0
T144	3122	7	0	0
T145	10438	52	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	972	0	0
T51	16268	12	0	0
T94	4962	14	0	0
T95	2176	8	0	0
T105	3945	3	0	0
T126	24983	51	0	0
T130	14548	38	0	0
T143	12449	55	0	0
T144	3122	6	0	0
T145	10438	45	0	0
T149	3057	7	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1083	0	0
T51	16268	10	0	0
T94	4962	2	0	0
T95	2176	6	0	0
T105	3945	5	0	0
T107	9279	6	0	0
T126	24983	36	0	0
T130	14548	45	0	0
T142	5543	18	0	0
T143	12449	48	0	0
T144	3122	12	0	0