Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	252124360	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

198864786

1

T1

359044

T2

203458

T3

100178

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	237817933	1			T1	467263		T2	257331		T3	128070
values[0x0]	102495392	1			T1	215157		T2	112047		T3	553234
values[0x1]	110675821	1			T1	233258		T2	120258		T3	603558

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	196607997	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

254381149

1

T1

481142

T2

266014

T3

131848

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1368103	1			T1	3579		T2	1879		T3	9624
valid_sources[0x01]	1516151	1			T1	3547		T2	1946		T3	9396
valid_sources[0x02]	1370728	1			T1	3645		T2	2041		T3	9379
valid_sources[0x03]	1354962	1			T1	3624		T2	1893		T3	9545
valid_sources[0x04]	1353865	1			T1	3609		T2	1988		T3	9537
valid_sources[0x05]	1362075	1			T1	3613		T2	1896		T3	9646
valid_sources[0x06]	1356690	1			T1	3589		T2	1806		T3	9450
valid_sources[0x07]	1353247	1			T1	3466		T2	1813		T3	9629
valid_sources[0x08]	1348002	1			T1	3610		T2	2027		T3	9529
valid_sources[0x09]	2232944	1			T1	3524		T2	1950		T3	9607
valid_sources[0x0a]	1352464	1			T1	3468		T2	2074		T3	9458
valid_sources[0x0b]	2206199	1			T1	3501		T2	1909		T3	9415
valid_sources[0x0c]	1481430	1			T1	3579		T2	1923		T3	9597
valid_sources[0x0d]	1349365	1			T1	3385		T2	1907		T3	9682
valid_sources[0x0e]	3778270	1			T1	3711		T2	1873		T3	9507
valid_sources[0x0f]	1353993	1			T1	3542		T2	1837		T3	9600
valid_sources[0x10]	1350377	1			T1	3470		T2	1837		T3	9304
valid_sources[0x11]	1396518	1			T1	3521		T2	1836		T3	9460
valid_sources[0x12]	1362000	1			T1	3734		T2	1912		T3	9472
valid_sources[0x13]	1999781	1			T1	3536		T2	1929		T3	9609
valid_sources[0x14]	1352810	1			T1	3509		T2	1888		T3	9500
valid_sources[0x15]	1354667	1			T1	3565		T2	1987		T3	9558
valid_sources[0x16]	1354067	1			T1	3578		T2	1964		T3	9732
valid_sources[0x17]	4708725	1			T1	3575		T2	2063		T3	9169
valid_sources[0x18]	1349027	1			T1	3639		T2	1910		T3	9502
valid_sources[0x19]	2209886	1			T1	3472		T2	2035		T3	9380
valid_sources[0x1a]	1440104	1			T1	3612		T2	1923		T3	9695
valid_sources[0x1b]	3511981	1			T1	3522		T2	1866		T3	9552
valid_sources[0x1c]	1832139	1			T1	3570		T2	2079		T3	9500
valid_sources[0x1d]	2096605	1			T1	3673		T2	1879		T3	9413
valid_sources[0x1e]	2586521	1			T1	3547		T2	1889		T3	9376
valid_sources[0x1f]	1356931	1			T1	3453		T2	1834		T3	9381
valid_sources[0x20]	1497788	1			T1	3501		T2	1943		T3	9540
valid_sources[0x21]	1353675	1			T1	3581		T2	1900		T3	9648
valid_sources[0x22]	1358689	1			T1	3587		T2	1878		T3	9512
valid_sources[0x23]	1585493	1			T1	3508		T2	1743		T3	9587
valid_sources[0x24]	1356044	1			T1	3618		T2	1780		T3	9474
valid_sources[0x25]	2391827	1			T1	3471		T2	1860		T3	9356
valid_sources[0x26]	1385758	1			T1	3536		T2	1876		T3	9489
valid_sources[0x27]	2524213	1			T1	3475		T2	1943		T3	9390
valid_sources[0x28]	1353348	1			T1	3521		T2	2122		T3	9572
valid_sources[0x29]	1359288	1			T1	3672		T2	2065		T3	9745
valid_sources[0x2a]	4555111	1			T1	3475		T2	1944		T3	9440
valid_sources[0x2b]	1351832	1			T1	3565		T2	1955		T3	9613
valid_sources[0x2c]	1359870	1			T1	3427		T2	1912		T3	9444
valid_sources[0x2d]	1359718	1			T1	3494		T2	1967		T3	9505
valid_sources[0x2e]	1360154	1			T1	3510		T2	1946		T3	9614
valid_sources[0x2f]	1360720	1			T1	3603		T2	1880		T3	9277
valid_sources[0x30]	1352621	1			T1	3628		T2	1856		T3	9556
valid_sources[0x31]	1691167	1			T1	3539		T2	1930		T3	9493
valid_sources[0x32]	1357069	1			T1	3489		T2	1766		T3	9585
valid_sources[0x33]	2274312	1			T1	3555		T2	1826		T3	9550
valid_sources[0x34]	1352353	1			T1	3709		T2	1795		T3	9443
valid_sources[0x35]	1811016	1			T1	3631		T2	1884		T3	9661
valid_sources[0x36]	1372209	1			T1	3561		T2	1965		T3	9097
valid_sources[0x37]	2215837	1			T1	3598		T2	2060		T3	9406
valid_sources[0x38]	1355558	1			T1	3592		T2	1822		T3	9221
valid_sources[0x39]	1353037	1			T1	3609		T2	1960		T3	9513
valid_sources[0x3a]	2357713	1			T1	3405		T2	1896		T3	9277
valid_sources[0x3b]	1354733	1			T1	3636		T2	1768		T3	9594
valid_sources[0x3c]	1354889	1			T1	3597		T2	1943		T3	9458
valid_sources[0x3d]	1383429	1			T1	3475		T2	2025		T3	9601
valid_sources[0x3e]	1606220	1			T1	3674		T2	2009		T3	9210
valid_sources[0x3f]	1350284	1			T1	3461		T2	1845		T3	9387
valid_sources[0x40]	2224666	1			T1	3575		T2	1940		T3	9581
valid_sources[0x41]	1346046	1			T1	3503		T2	1900		T3	9621
valid_sources[0x42]	5850333	1			T1	3754		T2	1863		T3	9471
valid_sources[0x43]	1458897	1			T1	3730		T2	1918		T3	9445
valid_sources[0x44]	3109117	1			T1	3477		T2	2058		T3	9505
valid_sources[0x45]	1780157	1			T1	3541		T2	1980		T3	9632
valid_sources[0x46]	1351270	1			T1	3594		T2	1925		T3	9510
valid_sources[0x47]	1408723	1			T1	3587		T2	1859		T3	9577
valid_sources[0x48]	1360489	1			T1	3694		T2	1958		T3	9623
valid_sources[0x49]	1351375	1			T1	3590		T2	1919		T3	9289
valid_sources[0x4a]	1351441	1			T1	3570		T2	1779		T3	9655
valid_sources[0x4b]	1349227	1			T1	3593		T2	1961		T3	9649
valid_sources[0x4c]	6694448	1			T1	3622		T2	1900		T3	9554
valid_sources[0x4d]	1349735	1			T1	3572		T2	1824		T3	9430
valid_sources[0x4e]	1814477	1			T1	3562		T2	1822		T3	9672
valid_sources[0x4f]	1443059	1			T1	3608		T2	1919		T3	9734
valid_sources[0x50]	1350566	1			T1	3679		T2	1903		T3	9318
valid_sources[0x51]	1351511	1			T1	3479		T2	1876		T3	9733
valid_sources[0x52]	1356635	1			T1	3556		T2	1823		T3	9555
valid_sources[0x53]	3765409	1			T1	3690		T2	1881		T3	9609
valid_sources[0x54]	1360641	1			T1	3704		T2	2002		T3	9682
valid_sources[0x55]	1357055	1			T1	3608		T2	1816		T3	9513
valid_sources[0x56]	1353738	1			T1	3821		T2	1817		T3	9439
valid_sources[0x57]	1522098	1			T1	3682		T2	1971		T3	9502
valid_sources[0x58]	1353101	1			T1	3512		T2	1938		T3	9646
valid_sources[0x59]	1382171	1			T1	3640		T2	1878		T3	9421
valid_sources[0x5a]	1359929	1			T1	3508		T2	1908		T3	9393
valid_sources[0x5b]	1354885	1			T1	3549		T2	1795		T3	9555
valid_sources[0x5c]	1354383	1			T1	3670		T2	1809		T3	9583
valid_sources[0x5d]	1350880	1			T1	3495		T2	1831		T3	9419
valid_sources[0x5e]	3552055	1			T1	3654		T2	2059		T3	9577
valid_sources[0x5f]	3417767	1			T1	3480		T2	1842		T3	9627
valid_sources[0x60]	1355163	1			T1	3627		T2	1820		T3	9534
valid_sources[0x61]	1826429	1			T1	3705		T2	1935		T3	9678
valid_sources[0x62]	1374895	1			T1	3438		T2	1833		T3	9606
valid_sources[0x63]	1350624	1			T1	3618		T2	1980		T3	9760
valid_sources[0x64]	1357162	1			T1	3451		T2	1833		T3	9665
valid_sources[0x65]	1355331	1			T1	3638		T2	1796		T3	9754
valid_sources[0x66]	1354229	1			T1	3659		T2	2077		T3	9356
valid_sources[0x67]	1360410	1			T1	3569		T2	1994		T3	9570
valid_sources[0x68]	1352069	1			T1	3500		T2	1788		T3	9787
valid_sources[0x69]	1472700	1			T1	3666		T2	1733		T3	9536
valid_sources[0x6a]	1517931	1			T1	3619		T2	1943		T3	9507
valid_sources[0x6b]	1349501	1			T1	3445		T2	1844		T3	9475
valid_sources[0x6c]	1347082	1			T1	3669		T2	1911		T3	9625
valid_sources[0x6d]	1345104	1			T1	3651		T2	1965		T3	9653
valid_sources[0x6e]	2582583	1			T1	3623		T2	1691		T3	9626
valid_sources[0x6f]	1354138	1			T1	3485		T2	1967		T3	9671
valid_sources[0x70]	1418405	1			T1	3654		T2	1952		T3	9318
valid_sources[0x71]	1354645	1			T1	3528		T2	1926		T3	9420
valid_sources[0x72]	1353807	1			T1	3466		T2	1982		T3	9469
valid_sources[0x73]	3857605	1			T1	3617		T2	1866		T3	9598
valid_sources[0x74]	3828491	1			T1	3612		T2	2024		T3	9607
valid_sources[0x75]	1355021	1			T1	3531		T2	1884		T3	9500
valid_sources[0x76]	1356780	1			T1	3535		T2	1756		T3	9594
valid_sources[0x77]	1360842	1			T1	3463		T2	1967		T3	9339
valid_sources[0x78]	1356168	1			T1	3589		T2	1857		T3	9506
valid_sources[0x79]	1352098	1			T1	3603		T2	1975		T3	9586
valid_sources[0x7a]	1355902	1			T1	3545		T2	2042		T3	9496
valid_sources[0x7b]	2281089	1			T1	3682		T2	2053		T3	9568
valid_sources[0x7c]	1352316	1			T1	3526		T2	2067		T3	9387
valid_sources[0x7d]	1366320	1			T1	3576		T2	1968		T3	9769
valid_sources[0x7e]	1357134	1			T1	3519		T2	2001		T3	9534
valid_sources[0x7f]	1517929	1			T1	3730		T2	1999		T3	9566
valid_sources[0x80]	1402146	1			T1	3563		T2	2032		T3	9650

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

86446019

1

T1

133633

T2

84269

T3

429145

values[0x0]

all_enables

biggest_size

60463870

1

T1

122080

T2

64409

T3

310407

values[0x1]

all_enables

biggest_size

51954897

1

T1

103331

T2

54780

T3

262229