Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

252137221

1

T1

556634

T2

286178

T3

143571

full_word

198865501

1

T1

359044

T2

203458

T3

100178

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	451002452	1			T1	915678		T2	489636		T3	243749
auto[TlIntgErrCmd]	96	1			T54	5		T113	6		T114	10
auto[TlIntgErrData]	84	1			T54	4		T113	7		T114	3
auto[TlIntgErrBoth]	90	1			T54	1		T113	7		T114	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

237820407

1

T1

467263

T2

257331

T3

128070

auto[1]

213182315

1

T1

448415

T2

232305

T3

115679

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	151374085	1			T1	333630		T2	173062		T3	851555
auto[TlIntgErrNone]	partial	auto[1]	100762891	1			T1	223004		T2	113116		T3	584156
auto[TlIntgErrNone]	full_word	auto[0]	86446195	1			T1	133633		T2	84269		T3	429145
auto[TlIntgErrNone]	full_word	auto[1]	112419281	1			T1	225411		T2	119189		T3	572636
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T54	3		T113	1		T114	5
auto[TlIntgErrCmd]	partial	auto[1]	45	1			T54	2		T113	3		T114	5
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T113	1		T175	1		T172	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T113	1		T130	1		T175	1
auto[TlIntgErrData]	partial	auto[0]	39	1			T54	2		T113	3		T114	2
auto[TlIntgErrData]	partial	auto[1]	36	1			T54	1		T113	3		T114	1
auto[TlIntgErrData]	full_word	auto[0]	6	1			T113	1		T130	2		T145	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T54	1		T172	1		T176	1
auto[TlIntgErrBoth]	partial	auto[0]	34	1			T113	2		T114	2		T130	3
auto[TlIntgErrBoth]	partial	auto[1]	49	1			T54	1		T113	4		T114	5
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T176	1		T177	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T113	1		T130	1		T173	1