Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	2874	0	0
entropy_period_rd_A	2147483647	1976	0	0
intr_enable_rd_A	2147483647	2289	0	0
prefix_0_rd_A	2147483647	1617	0	0
prefix_10_rd_A	2147483647	1562	0	0
prefix_1_rd_A	2147483647	1581	0	0
prefix_2_rd_A	2147483647	1636	0	0
prefix_3_rd_A	2147483647	1624	0	0
prefix_4_rd_A	2147483647	1605	0	0
prefix_5_rd_A	2147483647	1641	0	0
prefix_6_rd_A	2147483647	1689	0	0
prefix_7_rd_A	2147483647	1513	0	0
prefix_8_rd_A	2147483647	1558	0	0
prefix_9_rd_A	2147483647	1577	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2874	0	0
T53	3142	102	0	0
T54	5347	1	0	0
T55	6156	112	0	0
T98	6770	4	0	0
T114	24271	5	0	0
T115	1937	47	0	0
T116	7201	117	0	0
T126	3561	83	0	0
T129	7649	2	0	0
T130	9533	2	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1976	0	0
T100	5544	18	0	0
T114	24271	128	0	0
T129	7649	25	0	0
T140	6085	12	0	0
T141	2716	1	0	0
T142	7453	12	0	0
T143	2384	10	0	0
T144	48034	474	0	0
T145	12017	60	0	0
T146	2576	9	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2289	0	0
T100	5544	21	0	0
T114	24271	176	0	0
T129	7649	23	0	0
T140	6085	18	0	0
T142	7453	5	0	0
T143	2384	5	0	0
T147	1363	10	0	0
T148	1069	13	0	0
T149	1594	10	0	0
T150	1243	8	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1617	0	0
T100	5544	23	0	0
T114	24271	70	0	0
T129	7649	15	0	0
T140	6085	15	0	0
T141	2716	6	0	0
T142	7453	5	0	0
T143	2384	9	0	0
T144	48034	423	0	0
T145	12017	25	0	0
T146	2576	6	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1562	0	0
T100	5544	22	0	0
T114	24271	65	0	0
T129	7649	22	0	0
T140	6085	24	0	0
T141	2716	2	0	0
T142	7453	2	0	0
T143	2384	2	0	0
T144	48034	406	0	0
T145	12017	38	0	0
T146	2576	8	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1581	0	0
T100	5544	11	0	0
T114	24271	69	0	0
T129	7649	9	0	0
T140	6085	12	0	0
T141	2716	3	0	0
T142	7453	9	0	0
T143	2384	2	0	0
T144	48034	433	0	0
T145	12017	49	0	0
T146	2576	4	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1636	0	0
T100	5544	18	0	0
T114	24271	56	0	0
T129	7649	18	0	0
T140	6085	5	0	0
T141	2716	3	0	0
T142	7453	7	0	0
T143	2384	4	0	0
T144	48034	465	0	0
T145	12017	37	0	0
T146	2576	3	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1624	0	0
T100	5544	9	0	0
T114	24271	56	0	0
T123	12085	3	0	0
T129	7649	16	0	0
T140	6085	28	0	0
T141	2716	2	0	0
T142	7453	4	0	0
T143	2384	1	0	0
T144	48034	479	0	0
T145	12017	39	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1605	0	0
T100	5544	24	0	0
T114	24271	57	0	0
T129	7649	26	0	0
T140	6085	8	0	0
T142	7453	16	0	0
T143	2384	5	0	0
T144	48034	414	0	0
T145	12017	31	0	0
T151	2181	5	0	0
T152	10342	37	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1641	0	0
T100	5544	18	0	0
T114	24271	66	0	0
T129	7649	24	0	0
T140	6085	15	0	0
T141	2716	4	0	0
T142	7453	8	0	0
T144	48034	473	0	0
T145	12017	35	0	0
T151	2181	1	0	0
T152	10342	25	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1689	0	0
T100	5544	25	0	0
T114	24271	73	0	0
T129	7649	11	0	0
T140	6085	5	0	0
T141	2716	1	0	0
T142	7453	15	0	0
T143	2384	2	0	0
T144	48034	399	0	0
T145	12017	51	0	0
T146	2576	5	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1513	0	0
T100	5544	14	0	0
T114	24271	98	0	0
T129	7649	18	0	0
T140	6085	22	0	0
T141	2716	2	0	0
T142	7453	20	0	0
T143	2384	4	0	0
T144	48034	392	0	0
T145	12017	36	0	0
T146	2576	8	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1558	0	0
T100	5544	32	0	0
T114	24271	82	0	0
T129	7649	9	0	0
T140	6085	6	0	0
T141	2716	10	0	0
T142	7453	17	0	0
T143	2384	8	0	0
T144	48034	440	0	0
T145	12017	23	0	0
T146	2576	8	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1577	0	0
T100	5544	11	0	0
T114	24271	92	0	0
T129	7649	20	0	0
T140	6085	18	0	0
T141	2716	3	0	0
T142	7453	15	0	0
T143	2384	3	0	0
T144	48034	412	0	0
T145	12017	30	0	0
T146	2576	4	0	0