SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[kmac_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 308265609 | 1 | T1 | 1081 | T2 | 668186 | T3 | 1275 | ||||
auto[1] | 144667761 | 1 | T1 | 1517 | T2 | 242798 | T3 | 6033 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 452933207 | 1 | T1 | 2598 | T2 | 910984 | T3 | 7308 | ||||
values[1] | 21 | 1 | T112 | 1 | T145 | 2 | T168 | 1 | ||||
values[2] | 2 | 1 | T113 | 2 | - | - | - | - | ||||
values[3] | 77 | 1 | T111 | 4 | T112 | 3 | T113 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 452933210 | 1 | T1 | 2598 | T2 | 910984 | T3 | 7308 | ||||
values[1] | 11 | 1 | T111 | 2 | T113 | 1 | T169 | 1 | ||||
values[2] | 3 | 1 | T111 | 1 | T113 | 1 | T169 | 1 | ||||
values[3] | 87 | 1 | T111 | 6 | T112 | 5 | T113 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 452933120 | 1 | T1 | 2598 | T2 | 910984 | T3 | 7308 | ||||
auto[TlIntgErrCmd] | 90 | 1 | T111 | 7 | T112 | 3 | T113 | 7 | ||||
auto[TlIntgErrData] | 87 | 1 | T111 | 9 | T112 | 2 | T113 | 6 | ||||
auto[TlIntgErrBoth] | 73 | 1 | T111 | 4 | T112 | 5 | T113 | 7 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |