Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

253852999

1

T1

406

T2

550922

T3

1119

full_word

199080371

1

T1

2192

T2

360062

T3

6189

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	452933120	1			T1	2598		T2	910984		T3	7308
auto[TlIntgErrCmd]	90	1			T111	7		T112	3		T113	7
auto[TlIntgErrData]	87	1			T111	9		T112	2		T113	6
auto[TlIntgErrBoth]	73	1			T111	4		T112	5		T113	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

238611187

1

T1

1751

T2

464927

T3

2148

auto[1]

214322183

1

T1

847

T2

446057

T3

5160

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	152135577	1			T1	219		T2	331414		T3	1073
auto[TlIntgErrNone]	partial	auto[1]	101717191	1			T1	187		T2	219508		T3	46
auto[TlIntgErrNone]	full_word	auto[0]	86475494	1			T1	1532		T2	133513		T3	1075
auto[TlIntgErrNone]	full_word	auto[1]	112604858	1			T1	660		T2	226549		T3	5114
auto[TlIntgErrCmd]	partial	auto[0]	29	1			T113	2		T145	1		T170	1
auto[TlIntgErrCmd]	partial	auto[1]	53	1			T111	5		T112	3		T113	4
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T111	1		T113	1		T169	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T111	1		T169	1		T171	1
auto[TlIntgErrData]	partial	auto[0]	40	1			T111	3		T112	1		T113	3
auto[TlIntgErrData]	partial	auto[1]	40	1			T111	4		T112	1		T113	3
auto[TlIntgErrData]	full_word	auto[0]	5	1			T111	1		T171	1		T172	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T111	1		T173	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	37	1			T111	2		T112	3		T113	4
auto[TlIntgErrBoth]	partial	auto[1]	32	1			T111	2		T112	1		T113	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T112	1		T113	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T173	1		T174	1		-	-