Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : sha3pad_assert_if
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_cov_0/sha3pad_assert_if.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.sha3pad_assert_cov_if 100.00 100.00



Module Instance : tb.dut.sha3pad_assert_cov_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.24 96.27 93.33 100.00 100.00 93.85 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : sha3pad_assert_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
ProcessToRun_A 2147483647 345151 0 0
RunThenComplete_M 2147483647 3078822 0 0


ProcessToRun_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 345151 0 0
T1 29254 13 0 0
T2 186329 390 0 0
T3 16000 3 0 0
T12 257545 2337 0 0
T13 848825 100 0 0
T14 141195 150 0 0
T15 89152 38 0 0
T16 429911 92 0 0
T17 17039 9 0 0
T18 0 9 0 0
T19 1168 0 0 0

RunThenComplete_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 3078822 0 0
T1 29254 33 0 0
T2 186329 5542 0 0
T3 16000 150 0 0
T12 257545 13147 0 0
T13 848825 509 0 0
T14 141195 816 0 0
T15 89152 203 0 0
T16 429911 502 0 0
T17 17039 31 0 0
T18 0 31 0 0
T19 1168 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%