Line Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_reqfifo
| Total | Covered | Percent |
Conditions | 16 | 11 | 68.75 |
Logical | 16 | 11 | 68.75 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T12,T13 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
205271975 |
0 |
0 |
T1 |
29254 |
381 |
0 |
0 |
T2 |
186329 |
220568 |
0 |
0 |
T3 |
16000 |
4981 |
0 |
0 |
T12 |
257545 |
252873 |
0 |
0 |
T13 |
848825 |
35732 |
0 |
0 |
T14 |
141195 |
70308 |
0 |
0 |
T15 |
89152 |
5614 |
0 |
0 |
T16 |
429911 |
9741 |
0 |
0 |
T17 |
17039 |
273 |
0 |
0 |
T18 |
0 |
256 |
0 |
0 |
T19 |
1168 |
0 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
29254 |
29193 |
0 |
0 |
T2 |
186329 |
186322 |
0 |
0 |
T3 |
16000 |
15906 |
0 |
0 |
T12 |
257545 |
257544 |
0 |
0 |
T13 |
848825 |
848731 |
0 |
0 |
T14 |
141195 |
141189 |
0 |
0 |
T15 |
89152 |
89062 |
0 |
0 |
T16 |
429911 |
429839 |
0 |
0 |
T17 |
17039 |
16966 |
0 |
0 |
T19 |
1168 |
1103 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
29254 |
29193 |
0 |
0 |
T2 |
186329 |
186322 |
0 |
0 |
T3 |
16000 |
15906 |
0 |
0 |
T12 |
257545 |
257544 |
0 |
0 |
T13 |
848825 |
848731 |
0 |
0 |
T14 |
141195 |
141189 |
0 |
0 |
T15 |
89152 |
89062 |
0 |
0 |
T16 |
429911 |
429839 |
0 |
0 |
T17 |
17039 |
16966 |
0 |
0 |
T19 |
1168 |
1103 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
29254 |
29193 |
0 |
0 |
T2 |
186329 |
186322 |
0 |
0 |
T3 |
16000 |
15906 |
0 |
0 |
T12 |
257545 |
257544 |
0 |
0 |
T13 |
848825 |
848731 |
0 |
0 |
T14 |
141195 |
141189 |
0 |
0 |
T15 |
89152 |
89062 |
0 |
0 |
T16 |
429911 |
429839 |
0 |
0 |
T17 |
17039 |
16966 |
0 |
0 |
T19 |
1168 |
1103 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
205271975 |
0 |
0 |
T1 |
29254 |
381 |
0 |
0 |
T2 |
186329 |
220568 |
0 |
0 |
T3 |
16000 |
4981 |
0 |
0 |
T12 |
257545 |
252873 |
0 |
0 |
T13 |
848825 |
35732 |
0 |
0 |
T14 |
141195 |
70308 |
0 |
0 |
T15 |
89152 |
5614 |
0 |
0 |
T16 |
429911 |
9741 |
0 |
0 |
T17 |
17039 |
273 |
0 |
0 |
T18 |
0 |
256 |
0 |
0 |
T19 |
1168 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 11 | 78.57 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 0 | 0 | |
CONT_ASSIGN | 108 | 1 | 0 | 0.00 |
ALWAYS | 111 | 2 | 1 | 50.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 0 | 0.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
|
unreachable |
108 |
0 |
1 |
111 |
1 |
1 |
112 |
0 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
0 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo
| Total | Covered | Percent |
Conditions | 13 | 5 | 38.46 |
Logical | 13 | 5 | 38.46 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Not Covered | |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Unreachable | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
5 |
71.43 |
TERNARY |
138 |
2 |
1 |
50.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
2 |
1 |
50.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Not Covered |
|
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
0 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
29254 |
29193 |
0 |
0 |
T2 |
186329 |
186322 |
0 |
0 |
T3 |
16000 |
15906 |
0 |
0 |
T12 |
257545 |
257544 |
0 |
0 |
T13 |
848825 |
848731 |
0 |
0 |
T14 |
141195 |
141189 |
0 |
0 |
T15 |
89152 |
89062 |
0 |
0 |
T16 |
429911 |
429839 |
0 |
0 |
T17 |
17039 |
16966 |
0 |
0 |
T19 |
1168 |
1103 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
29254 |
29193 |
0 |
0 |
T2 |
186329 |
186322 |
0 |
0 |
T3 |
16000 |
15906 |
0 |
0 |
T12 |
257545 |
257544 |
0 |
0 |
T13 |
848825 |
848731 |
0 |
0 |
T14 |
141195 |
141189 |
0 |
0 |
T15 |
89152 |
89062 |
0 |
0 |
T16 |
429911 |
429839 |
0 |
0 |
T17 |
17039 |
16966 |
0 |
0 |
T19 |
1168 |
1103 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
29254 |
29193 |
0 |
0 |
T2 |
186329 |
186322 |
0 |
0 |
T3 |
16000 |
15906 |
0 |
0 |
T12 |
257545 |
257544 |
0 |
0 |
T13 |
848825 |
848731 |
0 |
0 |
T14 |
141195 |
141189 |
0 |
0 |
T15 |
89152 |
89062 |
0 |
0 |
T16 |
429911 |
429839 |
0 |
0 |
T17 |
17039 |
16966 |
0 |
0 |
T19 |
1168 |
1103 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 13 | 12 | 92.31 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 0 | 0 | |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 0 | 0.00 |
ALWAYS | 111 | 1 | 1 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
|
unreachable |
101 |
1 |
1 |
108 |
0 |
1 |
111 |
1 |
1 |
112 |
|
unreachable |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_rspfifo
| Total | Covered | Percent |
Conditions | 17 | 8 | 47.06 |
Logical | 17 | 8 | 47.06 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Unreachable | |
1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | Unreachable | |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Not Covered | |
LINE 130
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Unreachable | |
LINE 130
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Unreachable | |
LINE 131
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Unreachable | |
1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
6 |
85.71 |
TERNARY |
130 |
1 |
1 |
100.00 |
TERNARY |
138 |
2 |
1 |
50.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?
Branches:
-1- | Status | Tests |
1 |
Unreachable |
|
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Unreachable |
|
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
0 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
29254 |
29193 |
0 |
0 |
T2 |
186329 |
186322 |
0 |
0 |
T3 |
16000 |
15906 |
0 |
0 |
T12 |
257545 |
257544 |
0 |
0 |
T13 |
848825 |
848731 |
0 |
0 |
T14 |
141195 |
141189 |
0 |
0 |
T15 |
89152 |
89062 |
0 |
0 |
T16 |
429911 |
429839 |
0 |
0 |
T17 |
17039 |
16966 |
0 |
0 |
T19 |
1168 |
1103 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
29254 |
29193 |
0 |
0 |
T2 |
186329 |
186322 |
0 |
0 |
T3 |
16000 |
15906 |
0 |
0 |
T12 |
257545 |
257544 |
0 |
0 |
T13 |
848825 |
848731 |
0 |
0 |
T14 |
141195 |
141189 |
0 |
0 |
T15 |
89152 |
89062 |
0 |
0 |
T16 |
429911 |
429839 |
0 |
0 |
T17 |
17039 |
16966 |
0 |
0 |
T19 |
1168 |
1103 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
29254 |
29193 |
0 |
0 |
T2 |
186329 |
186322 |
0 |
0 |
T3 |
16000 |
15906 |
0 |
0 |
T12 |
257545 |
257544 |
0 |
0 |
T13 |
848825 |
848731 |
0 |
0 |
T14 |
141195 |
141189 |
0 |
0 |
T15 |
89152 |
89062 |
0 |
0 |
T16 |
429911 |
429839 |
0 |
0 |
T17 |
17039 |
16966 |
0 |
0 |
T19 |
1168 |
1103 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_msgfifo.u_msgfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 14 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 2 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
120 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
130 |
1 |
1 |
131 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_msgfifo.u_msgfifo
| Total | Covered | Percent |
Conditions | 24 | 21 | 87.50 |
Logical | 24 | 21 | 87.50 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T23,T24 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T23,T24,T25 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 130
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 130
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T13,T15 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 131
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (72'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_msgfifo.u_msgfifo
| Line No. | Total | Covered | Percent |
Branches |
|
9 |
9 |
100.00 |
TERNARY |
130 |
2 |
2 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_msgfifo.u_msgfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
60589928 |
0 |
0 |
T1 |
29254 |
37 |
0 |
0 |
T2 |
186329 |
142424 |
0 |
0 |
T3 |
16000 |
5897 |
0 |
0 |
T12 |
257545 |
241576 |
0 |
0 |
T13 |
848825 |
9031 |
0 |
0 |
T14 |
141195 |
9893 |
0 |
0 |
T15 |
89152 |
5118 |
0 |
0 |
T16 |
429911 |
10450 |
0 |
0 |
T17 |
17039 |
224 |
0 |
0 |
T18 |
0 |
677 |
0 |
0 |
T19 |
1168 |
0 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
29254 |
29193 |
0 |
0 |
T2 |
186329 |
186322 |
0 |
0 |
T3 |
16000 |
15906 |
0 |
0 |
T12 |
257545 |
257544 |
0 |
0 |
T13 |
848825 |
848731 |
0 |
0 |
T14 |
141195 |
141189 |
0 |
0 |
T15 |
89152 |
89062 |
0 |
0 |
T16 |
429911 |
429839 |
0 |
0 |
T17 |
17039 |
16966 |
0 |
0 |
T19 |
1168 |
1103 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
29254 |
29193 |
0 |
0 |
T2 |
186329 |
186322 |
0 |
0 |
T3 |
16000 |
15906 |
0 |
0 |
T12 |
257545 |
257544 |
0 |
0 |
T13 |
848825 |
848731 |
0 |
0 |
T14 |
141195 |
141189 |
0 |
0 |
T15 |
89152 |
89062 |
0 |
0 |
T16 |
429911 |
429839 |
0 |
0 |
T17 |
17039 |
16966 |
0 |
0 |
T19 |
1168 |
1103 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
29254 |
29193 |
0 |
0 |
T2 |
186329 |
186322 |
0 |
0 |
T3 |
16000 |
15906 |
0 |
0 |
T12 |
257545 |
257544 |
0 |
0 |
T13 |
848825 |
848731 |
0 |
0 |
T14 |
141195 |
141189 |
0 |
0 |
T15 |
89152 |
89062 |
0 |
0 |
T16 |
429911 |
429839 |
0 |
0 |
T17 |
17039 |
16966 |
0 |
0 |
T19 |
1168 |
1103 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
60589928 |
0 |
0 |
T1 |
29254 |
37 |
0 |
0 |
T2 |
186329 |
142424 |
0 |
0 |
T3 |
16000 |
5897 |
0 |
0 |
T12 |
257545 |
241576 |
0 |
0 |
T13 |
848825 |
9031 |
0 |
0 |
T14 |
141195 |
9893 |
0 |
0 |
T15 |
89152 |
5118 |
0 |
0 |
T16 |
429911 |
10450 |
0 |
0 |
T17 |
17039 |
224 |
0 |
0 |
T18 |
0 |
677 |
0 |
0 |
T19 |
1168 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_reqfifo
| Total | Covered | Percent |
Conditions | 16 | 11 | 68.75 |
Logical | 16 | 11 | 68.75 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T12,T13 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
69540490 |
0 |
0 |
T1 |
29254 |
6414 |
0 |
0 |
T2 |
186329 |
22230 |
0 |
0 |
T3 |
16000 |
1052 |
0 |
0 |
T12 |
257545 |
646652 |
0 |
0 |
T13 |
848825 |
103034 |
0 |
0 |
T14 |
141195 |
183206 |
0 |
0 |
T15 |
89152 |
15004 |
0 |
0 |
T16 |
429911 |
29619 |
0 |
0 |
T17 |
17039 |
546 |
0 |
0 |
T18 |
0 |
546 |
0 |
0 |
T19 |
1168 |
0 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
29254 |
29193 |
0 |
0 |
T2 |
186329 |
186322 |
0 |
0 |
T3 |
16000 |
15906 |
0 |
0 |
T12 |
257545 |
257544 |
0 |
0 |
T13 |
848825 |
848731 |
0 |
0 |
T14 |
141195 |
141189 |
0 |
0 |
T15 |
89152 |
89062 |
0 |
0 |
T16 |
429911 |
429839 |
0 |
0 |
T17 |
17039 |
16966 |
0 |
0 |
T19 |
1168 |
1103 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
29254 |
29193 |
0 |
0 |
T2 |
186329 |
186322 |
0 |
0 |
T3 |
16000 |
15906 |
0 |
0 |
T12 |
257545 |
257544 |
0 |
0 |
T13 |
848825 |
848731 |
0 |
0 |
T14 |
141195 |
141189 |
0 |
0 |
T15 |
89152 |
89062 |
0 |
0 |
T16 |
429911 |
429839 |
0 |
0 |
T17 |
17039 |
16966 |
0 |
0 |
T19 |
1168 |
1103 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
29254 |
29193 |
0 |
0 |
T2 |
186329 |
186322 |
0 |
0 |
T3 |
16000 |
15906 |
0 |
0 |
T12 |
257545 |
257544 |
0 |
0 |
T13 |
848825 |
848731 |
0 |
0 |
T14 |
141195 |
141189 |
0 |
0 |
T15 |
89152 |
89062 |
0 |
0 |
T16 |
429911 |
429839 |
0 |
0 |
T17 |
17039 |
16966 |
0 |
0 |
T19 |
1168 |
1103 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
69540490 |
0 |
0 |
T1 |
29254 |
6414 |
0 |
0 |
T2 |
186329 |
22230 |
0 |
0 |
T3 |
16000 |
1052 |
0 |
0 |
T12 |
257545 |
646652 |
0 |
0 |
T13 |
848825 |
103034 |
0 |
0 |
T14 |
141195 |
183206 |
0 |
0 |
T15 |
89152 |
15004 |
0 |
0 |
T16 |
429911 |
29619 |
0 |
0 |
T17 |
17039 |
546 |
0 |
0 |
T18 |
0 |
546 |
0 |
0 |
T19 |
1168 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo
| Total | Covered | Percent |
Conditions | 16 | 10 | 62.50 |
Logical | 16 | 10 | 62.50 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
36085866 |
0 |
0 |
T1 |
29254 |
1434 |
0 |
0 |
T2 |
186329 |
22230 |
0 |
0 |
T3 |
16000 |
1052 |
0 |
0 |
T12 |
257545 |
144085 |
0 |
0 |
T13 |
848825 |
33409 |
0 |
0 |
T14 |
141195 |
59083 |
0 |
0 |
T15 |
89152 |
15004 |
0 |
0 |
T16 |
429911 |
29619 |
0 |
0 |
T17 |
17039 |
546 |
0 |
0 |
T18 |
0 |
546 |
0 |
0 |
T19 |
1168 |
0 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
29254 |
29193 |
0 |
0 |
T2 |
186329 |
186322 |
0 |
0 |
T3 |
16000 |
15906 |
0 |
0 |
T12 |
257545 |
257544 |
0 |
0 |
T13 |
848825 |
848731 |
0 |
0 |
T14 |
141195 |
141189 |
0 |
0 |
T15 |
89152 |
89062 |
0 |
0 |
T16 |
429911 |
429839 |
0 |
0 |
T17 |
17039 |
16966 |
0 |
0 |
T19 |
1168 |
1103 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
29254 |
29193 |
0 |
0 |
T2 |
186329 |
186322 |
0 |
0 |
T3 |
16000 |
15906 |
0 |
0 |
T12 |
257545 |
257544 |
0 |
0 |
T13 |
848825 |
848731 |
0 |
0 |
T14 |
141195 |
141189 |
0 |
0 |
T15 |
89152 |
89062 |
0 |
0 |
T16 |
429911 |
429839 |
0 |
0 |
T17 |
17039 |
16966 |
0 |
0 |
T19 |
1168 |
1103 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
29254 |
29193 |
0 |
0 |
T2 |
186329 |
186322 |
0 |
0 |
T3 |
16000 |
15906 |
0 |
0 |
T12 |
257545 |
257544 |
0 |
0 |
T13 |
848825 |
848731 |
0 |
0 |
T14 |
141195 |
141189 |
0 |
0 |
T15 |
89152 |
89062 |
0 |
0 |
T16 |
429911 |
429839 |
0 |
0 |
T17 |
17039 |
16966 |
0 |
0 |
T19 |
1168 |
1103 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
36085866 |
0 |
0 |
T1 |
29254 |
1434 |
0 |
0 |
T2 |
186329 |
22230 |
0 |
0 |
T3 |
16000 |
1052 |
0 |
0 |
T12 |
257545 |
144085 |
0 |
0 |
T13 |
848825 |
33409 |
0 |
0 |
T14 |
141195 |
59083 |
0 |
0 |
T15 |
89152 |
15004 |
0 |
0 |
T16 |
429911 |
29619 |
0 |
0 |
T17 |
17039 |
546 |
0 |
0 |
T18 |
0 |
546 |
0 |
0 |
T19 |
1168 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_rspfifo
| Total | Covered | Percent |
Conditions | 24 | 18 | 75.00 |
Logical | 24 | 18 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T12,T13 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T12,T13 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 130
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 130
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 131
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T12,T13 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
9 |
9 |
100.00 |
TERNARY |
130 |
2 |
2 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
69467040 |
0 |
0 |
T1 |
29254 |
6414 |
0 |
0 |
T2 |
186329 |
22230 |
0 |
0 |
T3 |
16000 |
1052 |
0 |
0 |
T12 |
257545 |
646652 |
0 |
0 |
T13 |
848825 |
103034 |
0 |
0 |
T14 |
141195 |
183206 |
0 |
0 |
T15 |
89152 |
15004 |
0 |
0 |
T16 |
429911 |
29619 |
0 |
0 |
T17 |
17039 |
546 |
0 |
0 |
T18 |
0 |
546 |
0 |
0 |
T19 |
1168 |
0 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
29254 |
29193 |
0 |
0 |
T2 |
186329 |
186322 |
0 |
0 |
T3 |
16000 |
15906 |
0 |
0 |
T12 |
257545 |
257544 |
0 |
0 |
T13 |
848825 |
848731 |
0 |
0 |
T14 |
141195 |
141189 |
0 |
0 |
T15 |
89152 |
89062 |
0 |
0 |
T16 |
429911 |
429839 |
0 |
0 |
T17 |
17039 |
16966 |
0 |
0 |
T19 |
1168 |
1103 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
29254 |
29193 |
0 |
0 |
T2 |
186329 |
186322 |
0 |
0 |
T3 |
16000 |
15906 |
0 |
0 |
T12 |
257545 |
257544 |
0 |
0 |
T13 |
848825 |
848731 |
0 |
0 |
T14 |
141195 |
141189 |
0 |
0 |
T15 |
89152 |
89062 |
0 |
0 |
T16 |
429911 |
429839 |
0 |
0 |
T17 |
17039 |
16966 |
0 |
0 |
T19 |
1168 |
1103 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
29254 |
29193 |
0 |
0 |
T2 |
186329 |
186322 |
0 |
0 |
T3 |
16000 |
15906 |
0 |
0 |
T12 |
257545 |
257544 |
0 |
0 |
T13 |
848825 |
848731 |
0 |
0 |
T14 |
141195 |
141189 |
0 |
0 |
T15 |
89152 |
89062 |
0 |
0 |
T16 |
429911 |
429839 |
0 |
0 |
T17 |
17039 |
16966 |
0 |
0 |
T19 |
1168 |
1103 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
69467040 |
0 |
0 |
T1 |
29254 |
6414 |
0 |
0 |
T2 |
186329 |
22230 |
0 |
0 |
T3 |
16000 |
1052 |
0 |
0 |
T12 |
257545 |
646652 |
0 |
0 |
T13 |
848825 |
103034 |
0 |
0 |
T14 |
141195 |
183206 |
0 |
0 |
T15 |
89152 |
15004 |
0 |
0 |
T16 |
429911 |
29619 |
0 |
0 |
T17 |
17039 |
546 |
0 |
0 |
T18 |
0 |
546 |
0 |
0 |
T19 |
1168 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
468532635 |
0 |
0 |
T1 |
29254 |
2674 |
0 |
0 |
T2 |
186329 |
910984 |
0 |
0 |
T3 |
16000 |
9976 |
0 |
0 |
T12 |
257545 |
243107 |
0 |
0 |
T13 |
848825 |
95239 |
0 |
0 |
T14 |
141195 |
184715 |
0 |
0 |
T15 |
89152 |
47376 |
0 |
0 |
T16 |
429911 |
84360 |
0 |
0 |
T17 |
17039 |
2204 |
0 |
0 |
T19 |
1168 |
18 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
29254 |
29193 |
0 |
0 |
T2 |
186329 |
186322 |
0 |
0 |
T3 |
16000 |
15906 |
0 |
0 |
T12 |
257545 |
257544 |
0 |
0 |
T13 |
848825 |
848731 |
0 |
0 |
T14 |
141195 |
141189 |
0 |
0 |
T15 |
89152 |
89062 |
0 |
0 |
T16 |
429911 |
429839 |
0 |
0 |
T17 |
17039 |
16966 |
0 |
0 |
T19 |
1168 |
1103 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
29254 |
29193 |
0 |
0 |
T2 |
186329 |
186322 |
0 |
0 |
T3 |
16000 |
15906 |
0 |
0 |
T12 |
257545 |
257544 |
0 |
0 |
T13 |
848825 |
848731 |
0 |
0 |
T14 |
141195 |
141189 |
0 |
0 |
T15 |
89152 |
89062 |
0 |
0 |
T16 |
429911 |
429839 |
0 |
0 |
T17 |
17039 |
16966 |
0 |
0 |
T19 |
1168 |
1103 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
29254 |
29193 |
0 |
0 |
T2 |
186329 |
186322 |
0 |
0 |
T3 |
16000 |
15906 |
0 |
0 |
T12 |
257545 |
257544 |
0 |
0 |
T13 |
848825 |
848731 |
0 |
0 |
T14 |
141195 |
141189 |
0 |
0 |
T15 |
89152 |
89062 |
0 |
0 |
T16 |
429911 |
429839 |
0 |
0 |
T17 |
17039 |
16966 |
0 |
0 |
T19 |
1168 |
1103 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1236 |
1236 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
851794584 |
0 |
0 |
T1 |
29254 |
11638 |
0 |
0 |
T2 |
186329 |
910984 |
0 |
0 |
T3 |
16000 |
7308 |
0 |
0 |
T12 |
257545 |
109378 |
0 |
0 |
T13 |
848825 |
261240 |
0 |
0 |
T14 |
141195 |
497127 |
0 |
0 |
T15 |
89152 |
41718 |
0 |
0 |
T16 |
429911 |
76240 |
0 |
0 |
T17 |
17039 |
2204 |
0 |
0 |
T19 |
1168 |
18 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
29254 |
29193 |
0 |
0 |
T2 |
186329 |
186322 |
0 |
0 |
T3 |
16000 |
15906 |
0 |
0 |
T12 |
257545 |
257544 |
0 |
0 |
T13 |
848825 |
848731 |
0 |
0 |
T14 |
141195 |
141189 |
0 |
0 |
T15 |
89152 |
89062 |
0 |
0 |
T16 |
429911 |
429839 |
0 |
0 |
T17 |
17039 |
16966 |
0 |
0 |
T19 |
1168 |
1103 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
29254 |
29193 |
0 |
0 |
T2 |
186329 |
186322 |
0 |
0 |
T3 |
16000 |
15906 |
0 |
0 |
T12 |
257545 |
257544 |
0 |
0 |
T13 |
848825 |
848731 |
0 |
0 |
T14 |
141195 |
141189 |
0 |
0 |
T15 |
89152 |
89062 |
0 |
0 |
T16 |
429911 |
429839 |
0 |
0 |
T17 |
17039 |
16966 |
0 |
0 |
T19 |
1168 |
1103 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
29254 |
29193 |
0 |
0 |
T2 |
186329 |
186322 |
0 |
0 |
T3 |
16000 |
15906 |
0 |
0 |
T12 |
257545 |
257544 |
0 |
0 |
T13 |
848825 |
848731 |
0 |
0 |
T14 |
141195 |
141189 |
0 |
0 |
T15 |
89152 |
89062 |
0 |
0 |
T16 |
429911 |
429839 |
0 |
0 |
T17 |
17039 |
16966 |
0 |
0 |
T19 |
1168 |
1103 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1236 |
1236 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
36249310 |
0 |
0 |
T1 |
29254 |
1434 |
0 |
0 |
T2 |
186329 |
22230 |
0 |
0 |
T3 |
16000 |
1052 |
0 |
0 |
T12 |
257545 |
144085 |
0 |
0 |
T13 |
848825 |
33409 |
0 |
0 |
T14 |
141195 |
59083 |
0 |
0 |
T15 |
89152 |
15004 |
0 |
0 |
T16 |
429911 |
29619 |
0 |
0 |
T17 |
17039 |
546 |
0 |
0 |
T18 |
0 |
546 |
0 |
0 |
T19 |
1168 |
0 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
29254 |
29193 |
0 |
0 |
T2 |
186329 |
186322 |
0 |
0 |
T3 |
16000 |
15906 |
0 |
0 |
T12 |
257545 |
257544 |
0 |
0 |
T13 |
848825 |
848731 |
0 |
0 |
T14 |
141195 |
141189 |
0 |
0 |
T15 |
89152 |
89062 |
0 |
0 |
T16 |
429911 |
429839 |
0 |
0 |
T17 |
17039 |
16966 |
0 |
0 |
T19 |
1168 |
1103 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
29254 |
29193 |
0 |
0 |
T2 |
186329 |
186322 |
0 |
0 |
T3 |
16000 |
15906 |
0 |
0 |
T12 |
257545 |
257544 |
0 |
0 |
T13 |
848825 |
848731 |
0 |
0 |
T14 |
141195 |
141189 |
0 |
0 |
T15 |
89152 |
89062 |
0 |
0 |
T16 |
429911 |
429839 |
0 |
0 |
T17 |
17039 |
16966 |
0 |
0 |
T19 |
1168 |
1103 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
29254 |
29193 |
0 |
0 |
T2 |
186329 |
186322 |
0 |
0 |
T3 |
16000 |
15906 |
0 |
0 |
T12 |
257545 |
257544 |
0 |
0 |
T13 |
848825 |
848731 |
0 |
0 |
T14 |
141195 |
141189 |
0 |
0 |
T15 |
89152 |
89062 |
0 |
0 |
T16 |
429911 |
429839 |
0 |
0 |
T17 |
17039 |
16966 |
0 |
0 |
T19 |
1168 |
1103 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1236 |
1236 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
69546734 |
0 |
0 |
T1 |
29254 |
6414 |
0 |
0 |
T2 |
186329 |
22230 |
0 |
0 |
T3 |
16000 |
1052 |
0 |
0 |
T12 |
257545 |
646652 |
0 |
0 |
T13 |
848825 |
103034 |
0 |
0 |
T14 |
141195 |
183206 |
0 |
0 |
T15 |
89152 |
15004 |
0 |
0 |
T16 |
429911 |
29619 |
0 |
0 |
T17 |
17039 |
546 |
0 |
0 |
T18 |
0 |
546 |
0 |
0 |
T19 |
1168 |
0 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
29254 |
29193 |
0 |
0 |
T2 |
186329 |
186322 |
0 |
0 |
T3 |
16000 |
15906 |
0 |
0 |
T12 |
257545 |
257544 |
0 |
0 |
T13 |
848825 |
848731 |
0 |
0 |
T14 |
141195 |
141189 |
0 |
0 |
T15 |
89152 |
89062 |
0 |
0 |
T16 |
429911 |
429839 |
0 |
0 |
T17 |
17039 |
16966 |
0 |
0 |
T19 |
1168 |
1103 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
29254 |
29193 |
0 |
0 |
T2 |
186329 |
186322 |
0 |
0 |
T3 |
16000 |
15906 |
0 |
0 |
T12 |
257545 |
257544 |
0 |
0 |
T13 |
848825 |
848731 |
0 |
0 |
T14 |
141195 |
141189 |
0 |
0 |
T15 |
89152 |
89062 |
0 |
0 |
T16 |
429911 |
429839 |
0 |
0 |
T17 |
17039 |
16966 |
0 |
0 |
T19 |
1168 |
1103 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
29254 |
29193 |
0 |
0 |
T2 |
186329 |
186322 |
0 |
0 |
T3 |
16000 |
15906 |
0 |
0 |
T12 |
257545 |
257544 |
0 |
0 |
T13 |
848825 |
848731 |
0 |
0 |
T14 |
141195 |
141189 |
0 |
0 |
T15 |
89152 |
89062 |
0 |
0 |
T16 |
429911 |
429839 |
0 |
0 |
T17 |
17039 |
16966 |
0 |
0 |
T19 |
1168 |
1103 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1236 |
1236 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
111753796 |
0 |
0 |
T1 |
29254 |
83 |
0 |
0 |
T2 |
186329 |
220568 |
0 |
0 |
T3 |
16000 |
7381 |
0 |
0 |
T12 |
257545 |
562032 |
0 |
0 |
T13 |
848825 |
11278 |
0 |
0 |
T14 |
141195 |
22129 |
0 |
0 |
T15 |
89152 |
5614 |
0 |
0 |
T16 |
429911 |
9741 |
0 |
0 |
T17 |
17039 |
273 |
0 |
0 |
T18 |
0 |
256 |
0 |
0 |
T19 |
1168 |
0 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
29254 |
29193 |
0 |
0 |
T2 |
186329 |
186322 |
0 |
0 |
T3 |
16000 |
15906 |
0 |
0 |
T12 |
257545 |
257544 |
0 |
0 |
T13 |
848825 |
848731 |
0 |
0 |
T14 |
141195 |
141189 |
0 |
0 |
T15 |
89152 |
89062 |
0 |
0 |
T16 |
429911 |
429839 |
0 |
0 |
T17 |
17039 |
16966 |
0 |
0 |
T19 |
1168 |
1103 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
29254 |
29193 |
0 |
0 |
T2 |
186329 |
186322 |
0 |
0 |
T3 |
16000 |
15906 |
0 |
0 |
T12 |
257545 |
257544 |
0 |
0 |
T13 |
848825 |
848731 |
0 |
0 |
T14 |
141195 |
141189 |
0 |
0 |
T15 |
89152 |
89062 |
0 |
0 |
T16 |
429911 |
429839 |
0 |
0 |
T17 |
17039 |
16966 |
0 |
0 |
T19 |
1168 |
1103 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
29254 |
29193 |
0 |
0 |
T2 |
186329 |
186322 |
0 |
0 |
T3 |
16000 |
15906 |
0 |
0 |
T12 |
257545 |
257544 |
0 |
0 |
T13 |
848825 |
848731 |
0 |
0 |
T14 |
141195 |
141189 |
0 |
0 |
T15 |
89152 |
89062 |
0 |
0 |
T16 |
429911 |
429839 |
0 |
0 |
T17 |
17039 |
16966 |
0 |
0 |
T19 |
1168 |
1103 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1236 |
1236 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
205298490 |
0 |
0 |
T1 |
29254 |
381 |
0 |
0 |
T2 |
186329 |
220568 |
0 |
0 |
T3 |
16000 |
4981 |
0 |
0 |
T12 |
257545 |
252873 |
0 |
0 |
T13 |
848825 |
35732 |
0 |
0 |
T14 |
141195 |
70308 |
0 |
0 |
T15 |
89152 |
5614 |
0 |
0 |
T16 |
429911 |
9741 |
0 |
0 |
T17 |
17039 |
273 |
0 |
0 |
T18 |
0 |
256 |
0 |
0 |
T19 |
1168 |
0 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
29254 |
29193 |
0 |
0 |
T2 |
186329 |
186322 |
0 |
0 |
T3 |
16000 |
15906 |
0 |
0 |
T12 |
257545 |
257544 |
0 |
0 |
T13 |
848825 |
848731 |
0 |
0 |
T14 |
141195 |
141189 |
0 |
0 |
T15 |
89152 |
89062 |
0 |
0 |
T16 |
429911 |
429839 |
0 |
0 |
T17 |
17039 |
16966 |
0 |
0 |
T19 |
1168 |
1103 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
29254 |
29193 |
0 |
0 |
T2 |
186329 |
186322 |
0 |
0 |
T3 |
16000 |
15906 |
0 |
0 |
T12 |
257545 |
257544 |
0 |
0 |
T13 |
848825 |
848731 |
0 |
0 |
T14 |
141195 |
141189 |
0 |
0 |
T15 |
89152 |
89062 |
0 |
0 |
T16 |
429911 |
429839 |
0 |
0 |
T17 |
17039 |
16966 |
0 |
0 |
T19 |
1168 |
1103 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
29254 |
29193 |
0 |
0 |
T2 |
186329 |
186322 |
0 |
0 |
T3 |
16000 |
15906 |
0 |
0 |
T12 |
257545 |
257544 |
0 |
0 |
T13 |
848825 |
848731 |
0 |
0 |
T14 |
141195 |
141189 |
0 |
0 |
T15 |
89152 |
89062 |
0 |
0 |
T16 |
429911 |
429839 |
0 |
0 |
T17 |
17039 |
16966 |
0 |
0 |
T19 |
1168 |
1103 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1236 |
1236 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |