Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	55052	0	0
entropy_period_rd_A	2147483647	1936	0	0
intr_enable_rd_A	2147483647	2944	0	0
prefix_0_rd_A	2147483647	1986	0	0
prefix_10_rd_A	2147483647	1828	0	0
prefix_1_rd_A	2147483647	2013	0	0
prefix_2_rd_A	2147483647	1915	0	0
prefix_3_rd_A	2147483647	2049	0	0
prefix_4_rd_A	2147483647	1935	0	0
prefix_5_rd_A	2147483647	2098	0	0
prefix_6_rd_A	2147483647	2009	0	0
prefix_7_rd_A	2147483647	1910	0	0
prefix_8_rd_A	2147483647	1961	0	0
prefix_9_rd_A	2147483647	1946	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	55052	0	0
T50	370853	38415	0	0
T51	0	13702	0	0
T52	0	4	0	0
T109	0	151	0	0
T110	0	62	0	0
T111	0	2	0	0
T114	0	157	0	0
T119	0	129	0	0
T120	0	147	0	0
T123	0	7	0	0
T124	52209	0	0	0
T125	41965	0	0	0
T126	75064	0	0	0
T127	69370	0	0	0
T128	24433	0	0	0
T129	934743	0	0	0
T130	290307	0	0	0
T131	16416	0	0	0
T132	1148	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1936	0	0
T93	6198	32	0	0
T97	6301	15	0	0
T99	3770	8	0	0
T111	22569	122	0	0
T112	11504	63	0	0
T141	10297	53	0	0
T142	11339	35	0	0
T143	1778	8	0	0
T144	3270	5	0	0
T145	14321	26	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2944	0	0
T93	6198	17	0	0
T111	22569	177	0	0
T112	11504	93	0	0
T115	967	6	0	0
T117	1724	25	0	0
T141	10297	48	0	0
T142	11339	45	0	0
T146	1591	9	0	0
T147	1488	14	0	0
T148	1181	21	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1986	0	0
T93	6198	30	0	0
T97	6301	33	0	0
T99	3770	16	0	0
T111	22569	75	0	0
T112	11504	47	0	0
T141	10297	35	0	0
T142	11339	44	0	0
T143	1778	10	0	0
T144	3270	4	0	0
T145	14321	14	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1828	0	0
T93	6198	47	0	0
T97	6301	15	0	0
T99	3770	13	0	0
T111	22569	43	0	0
T112	11504	45	0	0
T141	10297	18	0	0
T142	11339	19	0	0
T143	1778	9	0	0
T144	3270	13	0	0
T145	14321	17	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2013	0	0
T93	6198	32	0	0
T97	6301	18	0	0
T99	3770	15	0	0
T111	22569	81	0	0
T112	11504	48	0	0
T141	10297	34	0	0
T142	11339	76	0	0
T143	1778	6	0	0
T144	3270	11	0	0
T145	14321	14	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1915	0	0
T93	6198	20	0	0
T97	6301	8	0	0
T99	3770	12	0	0
T111	22569	92	0	0
T112	11504	43	0	0
T141	10297	19	0	0
T142	11339	4	0	0
T143	1778	5	0	0
T144	3270	9	0	0
T145	14321	40	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2049	0	0
T93	6198	42	0	0
T97	6301	15	0	0
T99	3770	12	0	0
T111	22569	53	0	0
T112	11504	51	0	0
T141	10297	54	0	0
T142	11339	42	0	0
T144	3270	9	0	0
T145	14321	25	0	0
T149	10199	36	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1935	0	0
T93	6198	32	0	0
T97	6301	27	0	0
T99	3770	10	0	0
T111	22569	71	0	0
T112	11504	51	0	0
T141	10297	34	0	0
T142	11339	36	0	0
T143	1778	5	0	0
T144	3270	13	0	0
T145	14321	26	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2098	0	0
T93	6198	29	0	0
T97	6301	15	0	0
T99	3770	5	0	0
T111	22569	79	0	0
T112	11504	51	0	0
T141	10297	52	0	0
T142	11339	45	0	0
T143	1778	5	0	0
T144	3270	8	0	0
T145	14321	11	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2009	0	0
T93	6198	28	0	0
T99	3770	11	0	0
T111	22569	87	0	0
T112	11504	55	0	0
T120	11052	4	0	0
T141	10297	51	0	0
T142	11339	71	0	0
T143	1778	3	0	0
T144	3270	8	0	0
T145	14321	4	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1910	0	0
T93	6198	39	0	0
T97	6301	16	0	0
T99	3770	5	0	0
T111	22569	76	0	0
T112	11504	32	0	0
T141	10297	8	0	0
T142	11339	60	0	0
T143	1778	3	0	0
T144	3270	7	0	0
T145	14321	13	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1961	0	0
T93	6198	30	0	0
T99	3770	17	0	0
T111	22569	88	0	0
T112	11504	43	0	0
T120	11052	9	0	0
T141	10297	43	0	0
T142	11339	63	0	0
T143	1778	6	0	0
T144	3270	12	0	0
T145	14321	13	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1946	0	0
T93	6198	25	0	0
T97	6301	17	0	0
T99	3770	7	0	0
T111	22569	81	0	0
T112	11504	35	0	0
T120	11052	8	0	0
T141	10297	27	0	0
T142	11339	30	0	0
T144	3270	7	0	0
T145	14321	22	0	0