Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

256409183

1

T1

23351

T2

10

T3

45790

full_word

197836940

1

T1

37166

T2

176

T3

80448

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	454245833	1			T1	60517		T2	186		T3	126238
auto[TlIntgErrCmd]	94	1			T122	3		T123	4		T124	5
auto[TlIntgErrData]	97	1			T122	5		T123	3		T124	8
auto[TlIntgErrBoth]	99	1			T122	2		T123	3		T124	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

240429361

1

T1

41431

T2

90

T3

89196

auto[1]

213816762

1

T1

19086

T2

96

T3

37042

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	153705934	1			T1	14960		T2	3		T3	29396
auto[TlIntgErrNone]	partial	auto[1]	102702985	1			T1	8391		T2	7		T3	16394
auto[TlIntgErrNone]	full_word	auto[0]	86723295	1			T1	26471		T2	87		T3	59800
auto[TlIntgErrNone]	full_word	auto[1]	111113619	1			T1	10695		T2	89		T3	20648
auto[TlIntgErrCmd]	partial	auto[0]	34	1			T122	2		T123	1		T124	3
auto[TlIntgErrCmd]	partial	auto[1]	54	1			T122	1		T123	3		T124	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T182	1		T183	1		T184	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T130	2		T185	1		-	-
auto[TlIntgErrData]	partial	auto[0]	50	1			T122	4		T123	2		T124	7
auto[TlIntgErrData]	partial	auto[1]	36	1			T122	1		T123	1		T124	1
auto[TlIntgErrData]	full_word	auto[0]	6	1			T186	1		T181	1		T182	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T166	1		T180	1		T182	1
auto[TlIntgErrBoth]	partial	auto[0]	33	1			T124	1		T130	5		T186	3
auto[TlIntgErrBoth]	partial	auto[1]	57	1			T122	2		T123	3		T124	5
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T124	1		T186	1		T166	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T166	1		T185	1		T187	1